Datorarkitektur 1. Sekventiella kretsar (minne) December 2008

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Kristina Lundström
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1 Datorarkitektur Sekventiella kretsar (minne) December 28

2 B M C A The function can be described by a thruth table. 4 Minterms The majority function

3 Tools such as Logisim can calculate the thruth table from a circuit...and minimize the expression using a Karnaugh map......and build the minimized circuit for us!

För en kombinatorisk krets gäller att det existerar en entydig kombination av utsignal-tillstånd för varje möjlig kombination av insignaler.

4 För en kombinatorisk krets gäller att det existerar en entydig kombination av utsignal-tillstånd för varje möjlig kombination av insignaler. En utsignal från en kombinatorisk krets beror ej av kretsens historia dvs tidigare in-signalvärden - kretsen saknar minne! Är detta en kombinatorisk krets? Därför kan kombinatoriska logiska kretsars funktion beskrivas med hjälp av sanningstabeller. register a 5 bit register b 5 bit register c 5 bit Registers 32 bit Vi har sett att vi kan 32 bit konstruera en ALU med hjälp av ALU OP kombinatoriska kretstar. 32 bit

5 Om det var en kombinatorisk krets skulle vi få samma utdata för samma indata varje gång register a 5 bit 32 bit register b 5 bit 32 Registers 32 bit En kombinatorisk krets kan inte ha feedback (återkoppling). ALU OP register c 5 bit 32 bit och vad är nu det här? På en och samma adress vill vi kunna lagra olika data vid olika tillfällen.

6 Vi behöver krestar med minne.

7 Q = when at least one of A and B equals Q = when both A and B equal A B Q Q Q = when at least one of A and B equals Q = when at least one of A or B equal

8 When Q is true, the bottom NOR-gate actcs like an inverter (no matter the value of S) and Q becomes false... What happens if we change to true here?... which becomes the input to the top NOR-gate Q = true = Q (Q is unchanged) A pair of cross-coupled NOR-gates.

9 What happens if we change back to false again? Asserting R will give Q = false which becomes the input to the bottom NORgate Q = true... which becomes the input to the upper NORgate Q = false

10 Deasserting R won t change anything, Q remains false no matter the value of R. What happens if we change to true here? When both R and S are deasserted, the cross-coupled NOR-gats remembers the values of Q and Q

11 What happens if we change S back to false?... which becomes the input to the top NOR-gate Q = true Asserting S gives Q = false...

12 Again, when both R and S are deasserted, the crosscoupled NOR-gats remembers the values of Q and Q Deasserting S won t change anything...

13 R S Q n+ Q n+ Q n Q n?? Logisim DEMO

14 R S Q n+ Q n+ both zero Q n Q n Overriding the memory feedback action. What happens if both R and S drops (voltage change is not instanteneous) to zero simultaneously?

15 R drops first resulting in Q = S drops first resulting in Q =

16 An example of sequential logic: The output output depends not only on the present input but also on the history of the input. R S Q n+ Q n+ Q n Q n Restricted If both R and S drops to zero at the same time metastability

17 R Q R S Q n+ Q n+ Q n Q n S Q Restricted A SR Latch (Set and Reset Latch) can store -bit of data.

18 SR Latch Setting C to will only reset Q if D is at the same time. D Latch D can only function as Set when C (clock/enable) is true.

19 C D Q n+ Q n+ Comment X Q n Q n No Change Reset Set

20 C Q A D Latch (Data Latch) can store -bit of data. D Q C D Q n+ Q n+ Comment X Q n Q n No Change Reset Set

21 R S Q Q A latch is a sequential device that watches all of its inputs continuously and changes its outputs at any time. R S SR Latch Q n+ Q n Q n+ Q n Restricted A flip-flop is a sequential device that samples its inputs and changes its outputs only at times determined by a clocking signal. C Q C D D Latch / Flip-Flop Q n+ Q n+ Comment D Q X Q n Q n No Change Reset Set

22 C Q C D Q n+ D Latch Q n+ Comment D Q X Q n Q n No Change Reset Set D C Q When the latch is open (C=) Q follows D (a transparent latch)

23 Changing C back to zero The output Q of the master latch follows input D when clock is high (which closes the slave latch).

24 Changing C back to zero opens the slave latch taking the Q output of the master latch as D input.

25 D C Q Output Q only changes on falling clock edges (non transparent).

26 C D Q n+ Q n+ Comment non-falling X Q n Q n No Change Set Reset

27 The triangle indicates an edge-trigged latch a flip flop. C Q A D Flip-Flop The inversion bubble on the clock input indicate a falling-edge triggered flip-flop D Q C D Q n+ Q n+ Comment non-falling X Q n Q n No Change Set Reset

28 Logisim DEMO 8 bit D flip-flop register

29 Clock 8 D Flip-Flops used to form a 8 bit register. 2 A falling edge trigged D flip-flop C Q D Q

30 Clock goes to high... output remains unchanged. 2

31 Clock falls back to low... output equals input. 2

32 Changing input... does not affect ouput. 2

33 Funkar bra med multiplexer eftersom vi har relativt få register. We have now built a complete register file. register a 3 bit 8 bit register b 3 bit Registers 8 bit ALU OP register c 3 bit 8 bit

34 MEMORY Varje cell har en unik adress. Fyra bytes bildar ett ord (word) om 32 bitar. Address xffffffff xfffffffe xfffffffd xfffffffc... x3 x2 x x Content I MIPS består minnet av 2 32 celler. Varje cell i minnet kan lagra åtta bitar, dvs en byte. Kan vi bygga minnet på samma sätt som register-filen?

35 32 stycken MEMORY 2 32 stycken Address xffffffff xfffffffe xfffffffd xfffffffc... x3 x2 x x Content Giant Multiplexor

36 Möjligt, men absolut inte praktiskt att bygga ut till 2 32 olika data inputs......och 32 select input.

37 All inputs share the same output line. What happens if we change to here? Signals are not or... Signals on the wire are high or low voltage. We cannot have high and low voltage at the same time. E = Error

38 Three State Buffer A B E A (low ) E (low) B High Z When not Enabled (E = ) the three state buffer acts lika a huge resistance, kind of cutting of the wire. (high) (low) High Z (low) (high) (high) (high) (low) (high) When Enabled (E = ) the three state buffer lets the input signal A through. Output B can be in three states, (low), (high) and high resistance (Z).

39 A tranistor is never completely off, only the number of electrons used to form the current can be controlled high or low current A three state buffer acts like a true switch compared to a transistor.

40 A multilexor Can use three state buffers to implement a multiplexor. A shared data line (bus).

41 4x2 SRAM Memory A D Flip-Flop Using three state buffer instead of multiplerxors make it possible to share data lines. A shared output data bus.

42 4x4 SRAM Memory Using three state buffer instead of multiplerxors make it easy to extend... Address line, aka word line. 4x8 bit = 32 bit = Word

43 Static Random Access Memory 4x4 SRAM Memory Random? Random: takes the same time to access any random memory location. Static?

Efter en tid "rinner" ellektronerna ut och kondensatorn tappar sin laddning.

44 En kondensator (Capacitor) är som en läckande hink med vatten. Kondensatorn fylls på med elektroner och laddas därmed upp. Efter en tid "rinner" ellektronerna ut och kondensatorn tappar sin laddning. Hmm, en kondensator borde kunna användas för att lagra en bit... Synd bara att den tappar sitt minne efter ett tag...

45 Transistor Word Line Capacitor Bit Line Asserting both the Word Line and the Bit Line charges the capacitor

46 Write: assert word line, drive new value (/) on bit line. Word Line Read: assert word line, sense value on bit line (destroys saved value) Bit Line Reading a bit destroys the bit must refresh the memory cell.

47 Word Lines Bit Cell High Bit Lines Sense Amplifier Low Address Data

48 bit line word line Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically A latch is used to remember a whole word line. because of this refresh requirement, it is a dynamic random access memory as opposed to SRAM and other static memory DRAM

49 Normal RAM drives many bits (row) out of array, selects few to output. Latch Adding latch at row outputs allows us to save an entire row of the RAM Later accesses to the RAM can eliminate the row access time, just need column access time Most common in DRAM, page-mode SRAMs also exist

50 SRAM DRAM Faster Stable - holds value as long as power applied Less dense (4-6 transistors/bit) More expensive per bit Unstable - needs refresh Slower High density ( ransistor/bit) Less expensive per bit Registers must be as fast as possible, hence Flip-Flop memory similar to SRAM is used for registers. Since we use quite a few registers, the low bit denisity does not matter that much.

51 John Von Neumann, who lived from , was working at the Institute for Advanced Study when he became fascinated by the success of the ENIAC. This fascination would lead him to undertake an abstract study of computation that showed that: a computer should have a very simple, fixed physical structure, and yet be able to execute any kind of computation by means of a proper programmed control without the need for any change in the unit itself.

52 John von Neuman 945: The stored program computer The von Neuman model

Ur den formella kursplanen: Efter genomgången kurs skall deltagarna ingående kunna beskriva funktionen hos och uppbyggnaden av en dators delar såsom

53 Ur den formella kursplanen: Efter genomgången kurs skall deltagarna ingående kunna beskriva funktionen hos och uppbyggnaden av en dators delar såsom -styrenhet - primärminne - in- och utmatningssystem Dessa saker börjar vi få hyffsad koll på... Deltagarna skall kunna programmera i assemblerspråk.

54 Jaha... Men enligt den informella kursplanen då? Hur kul som hellst! Vi får lära oss från grunden hur en dator egentligen fungerar. När jag gått kursen kan jag i princip springa ner på stan och köpa en säck transistorer, bygga en dator och programmera den.

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