VHDL Basics. Component model Code model Entity Architecture Identifiers and objects Operations for relations. Bengt Oelmann -- copyright

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1 BO 1 VHDL Basics Outline Component model Code model Entity Architecture Identifiers and objects Operations for relations Bengt Oelmann -- copyright Component model Model for describing components External interface Internal function Ports: external connections to the component VHDL-komponent A B C The component s - Behaviour or - Structure X Y Function: a number of parallel processes Bengt Oelmann -- copyright

2 BO 2 Code model VHDL-component Declaration of entity Interface - Entity with ports Declaration of architecture Function - architecture Bengt Oelmann -- copyright Declare the interface of the VHDLcomponent MUX 2-1 a b y sel entity mux2 is port ( a: in STD_LOGIC; b: in STD_LOGIC; sel: in STD_LOGIC; y: out STD_LOGIC; ); end mux2; Bengt Oelmann -- copyright

3 BO 3 The ports of the VHDL-component port defines inputs and outputs entity mux2 is port ( a: in STD_LOGIC; b: in STD_LOGIC; sel: in STD_LOGIC; y: out STD_LOGIC; ); end mux2; in/out defines the mode of the port Determines the direction of the dataflow std_logic is the datatype for the inputs and output Bengt Oelmann -- copyright Ports in VHDL Port-declaration is the most important thing in the entity-declaration Each port represents The external pins of the component Each port has a Port-name Mode Datatype An identifier that you create Direction of data Which values to port can be assigned Bengt Oelmann -- copyright

4 BO 4 The modes of the port IN The signal goes only in to the component and the value is driven by another component. The input signal is used on the right side in the assignment: z <= a OR inport OUT The signal goes out from the component. It is not possible to read the value of the output. Is used on the left side in the assignment: outport <= a OR b BUFFER The signal goes out from the component. It is not possible to read the value of the output. Can be used on both sides in the assignment: buffer_port <= a OR b; z <= buffer_port OR c; INOUT The signal can go in both directions, either in or out -The value of the signal can be read by the component -The signal can be driven by other components -Can be used in both sides in an assignment Bengt Oelmann -- copyright Describing the function in the architecture MUX 2-1 a b y sel architecture mux2_arch of mux2 is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2_arch; In the architecture the function is described: If sel is 0 then the value of a is put on the output y. Otherwise (sel=1) the value of b is put on the output y. Bengt Oelmann -- copyright

5 BO 5 Declaration of the architecture Name of the architecture Name of the entity begin end for the architecture architecture mux2_arch of mux2 is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2_arch; Process with sensitivity-list Sequential statements (if-then-else) in the process begin end for the process Bengt Oelmann -- copyright Structure of the architecture architecture name_arch of name is Declaration of signals begin Parallella satser Process 1 Signals are used for communication between components and parallel statements. Signals can only be declared at architecture-level (not in processes) Parallel statements Process 2 Inside a process the execution is sequential Parallel statements end name_arch; Processes and parallell statements are executed in parallel Bengt Oelmann -- copyright

6 BO 6 Example of parallel and sequential statements ENTITY ename IS Ports( a, b, c: IN bit; y, z, w: OUT bit; Deklarationer -- no variables allowed END ename ARCHITECTURE first OF ename IS Deklarationer -- no variables, but signals are OK BEGIN y <= a AND b; PROCESS (a,b,c) Deklarationer VARIABLE v: bit; BEGIN v := (a OR b); v := v AND c; w <= a XOR v; END PROCESS; -- no signals, but variables are OK Parallel processes Statements in processes are sequential z <= c XOR b; END first; Bengt Oelmann -- copyright Identifiers in VHDL Identifiers Are names on things that you create E.g. names for architectures, entities, processes, variables, signals Rules for naming Cannot be a reserved word in VHDL (e.g. for, if) VHDL is case-insensitive First character must be a letter Last character cannot be underscore (_) Two consecutive underscores are not allowed Bengt Oelmann -- copyright

7 BO 7 Objects in VHDL Objects can hold a value Objects have class and type Class determines what kind of operations can be performed on the object Type determines what values the object can hold Objects can be initialized (only for simulation) They are declared in entity, architecture, process, or package Bengt Oelmann -- copyright Classes in VHDL Signal Their values are changed as a function of time They have a signal-driver and can be seen upon as a wire Variable Their values are changed immediately after assignment No timing is related to variables Constant Their values cannot be changed File Values to and from external file can be accessed Bengt Oelmann -- copyright

8 BO 8 Datatypes in VHDL VHDL has hard requirements on typing Objects of different types cannot be mixed Functions for type-conversion must be used Two main categories of datatypes Scalar Can be assigned one single value Examples: enumeration, integer, float, physical Composite Can be assigned multiple values Examples: array, record Bengt Oelmann -- copyright Scalar Enumeration A list of discrete values the variable can be assigned to Ex: type weekday = (mon, tue, wed, thu, fri, sat, sun); Integer A set integers positive or negative A pre-defined datatype Integer is of 32-bits with sign 2 31 to +(2 31-1) When describing hardware a limited range can be used Ex: variable num: integer range 64 to 64 Bengt Oelmann -- copyright

9 BO 9 Scalar Floating-point Pre-defined datatype is real 32-bits single precision Is never used for describing hardware Will result in too complex hardware Physical Datatype for physical units Ex. time, ma, Volt Has no meaning for describing hardware Bengt Oelmann -- copyright Examples of enumerated datatypes Pre-defined types (1076) type boolean is (FALSE, TRUE); type bit is ( 0, 1 ); Pre-defined types (1164) Std_logic Std_ulogic Arrays of these types and sub-types Access to these types by including: LIBRARY ieee; USE ieee.std_logic_1164.all; Bengt Oelmann -- copyright

10 BO 10 Std_logic Definition av std_logic type std_ulogic is ( U, -- Uninitialized X -- Forcing unknown 0 -- Forcing zero 1 -- Forcing one Z -- High impedance W -- Weak unknown L -- Weak zero H -- Weak one - );-- Don t care subtype std_logic is resolved std_ulogic; library IEEE; use IEEE.std_logic_1164.all; First in the VHDL to include libraries (packages) Bengt Oelmann -- copyright Arrays Composite data types Examples of declarations of 8-bit vectors signal s1: bit_vector(7 downto 0); variable v1: bit_vector(7 downto 0); Assignment of the bit vector s1 <= ; v1 := ; Least significant bit Most significant bit Bengt Oelmann -- copyright

11 BO 11 Composite data types Ex: two-dimensional array type table6x2 is array (0 to 5, 1 downto 0) of bit; constant mytable: table6x2 := ( 00, 01, 10, 11, 01, 01 ); Ex: Bit vectors for binary, octal and hexadecimal numbers X A3 -- = B 1010_0011 for a 8-bits vector O = B 010_111 for a 6-bits vector Bengt Oelmann -- copyright Attribute Attribute Holds information about a signal, variable, data type, function. Example #1 type bitcount is integer range 3 to +5; bitcount left bitcount right bitcount low bitcount high Bengt Oelmann -- copyright

12 BO 12 Attribute Example #2 type byte is array (7 downto 0) of std_logic; byte left byte right byte low byte high i går från 7 ner till 0 Example #3 for i in byte high downto byte low loop v_byte(i) := 1 ; end loop; Bengt Oelmann -- copyright Operators in VHDL Operators for Relations Arithmetic operationer Symbol Operation = eual /= Un-equal < Less than > Greater than <= Less-equal >= Greater-equal Symbol Operation + addidion - subtraktion * multiplikation / division abs Absolute value rem remainder mod modulus ** exponent Supported by synthesis tools Bengt Oelmann -- copyright

13 BO 13 END of Lecture 2 Outline Component model Code model Entity Architecture Identifiers and objects Operations for relations Bengt Oelmann -- copyright