Digitalteknik och Datorarkitektur 5hp

Storlek: px

Starta visningen från sidan:

Download "Digitalteknik och Datorarkitektur 5hp"

Jonas Gunnarsson
för 7 år sedan
Visningar:

1 4 Minterms The majority function igitalteknik och atorarkitektur 5hp ekventiella kretsar 28 april 28 The function can be described by a thruth table A B M Tools such as Logisim can calculate the thruth table from a circuit För en kombinatorisk krets gäller att det existerar en entydig kombination av utsignal-tillstånd för varje möjlig kombination av insignaler and minimize the expression using a Karnaugh map and build the minimized circuit for us! En utsignal från en kombinatorisk krets beror ej av kretsens historia dvs tidigare in-signalvärden - kretsen saknar minne! Är detta en kombinatorisk krets? ärför kan kombinatoriska logiska kretsars funktion beskrivas med hjälp av sanningstabeller register a register b register c egisters Vi har sett att vi kan konstruera en ALU med hjälp av ALU OP kombinatoriska kretstar Om det var en kombinatorisk krets skulle vi få samma utdata för samma indata varje gång Vi behöver krestar med minne register a register b 32 egisters En kombinatorisk krets kan inte ha feedback (återkoppling) ALU OP register c och vad är nu det här? På en och samma adress vill vi kunna lagra olika data vid olika tillfällen

2 = when at least one of A and B equals When is true, the bottom NO-gate actcs like an inverter (no matter the value of ) and becomes false = when both A and B equal A B What happens if we change to true here? which becomes the input to the top NO-gate = true = ( is unchanged) = when at least one of A and B equals = when at least one of A or B equal A pair of cross-coupled NO-gates What happens if we change back to false again? Asserting will give = false easserting won t change anything, remains false no matter the value of which becomes the input to the bottom NOgate = true What happens if we change to true here? which becomes the input to the upper NOgate = false When both and are deasserted, the cross-coupled NO-gats remembers the values of and What happens if we change back to false? Again, when both and are deasserted, the crosscoupled NO-gats remembers the values of and which becomes the input to the top NO-gate = true Asserting gives = false easserting won t change anything 2

3 ?? Logisim EMO Overriding the memory feedback action both zero What happens if both and drops (voltage change is not instanteneous) to zero simultaneously? drops first resulting in = An example of sequential logic: The output output depends not only on the present input but also on the history of the input + + drops first resulting in = estricted If both and drops to zero at the same time metastability Latch + + estricted ting to will only reset if is at the same time can only function as when (clock/enable) is true Latch A Latch ( and Latch) can store -bit of data 3

4 A Latch (ata Latch) can store -bit of data + + omment + + omment No hange No hange A latch is a sequential device that watches all of its inputs continuously and changes its outputs at any time Latch + + estricted + Latch + omment No hange A flip-flop is a sequential device that samples its inputs and changes its outputs only at times determined by a clocking signal Latch / Flip-Flop + + omment No hange When the latch is open (=) follows (a transparent latch) hanging back to zero hanging back to zero The output of the master latch follows input when clock is high (which closes the slave latch) opens the slave latch taking the output of the master latch as input 4

5 non-falling + + omment No hange Output only changes on falling clock edges (non transparent) The triangle indicates an edge-trigged latch a flip flop A Flip-Flop The inversion bubble on the clock input indicate a falling-edge triggered flip-flop Logisim EMO + + omment 8 bit flip-flop register non-falling No hange lock 8 Flip-Flops used to form a 8 bit register lock goes to high output remains unchanged 2 A falling edge trigged flip-flop 2 5

6 lock falls back to low output equals input hanging input does not affect ouput 2 2 register a 3 bit register b 3 bit Funkar bra med multiplexer eftersom vi har relativt få register egisters We have now built a complete register file 8 bit 8 bit ALU OP Varje cell har en unik adress Fyra bytes bildar ett ord (word) om 32 bitar MEMOY Address ontent xffffffff xfffffffe xfffffff xfffffff x3 x2 x x I MIP består minnet av 2 32 celler Varje cell i minnet kan lagra åtta bitar, dvs en byte Kan vi bygga minnet på samma sätt som register-filen? register c 3 bit 8 bit 32 stycken MEMOY Address xffffffff ontent 2 32 stycken xfffffffe xfffffff xfffffff x3 x2 x x Giant Multiplexor Möjligt, men absolut inte praktiskt att bygga ut till 2 32 olika data inputs och 32 select input 6

7 All inputs share the same output line Three tate Buffer What happens if we change to here? ignals are not or ignals on the wire are high or low voltage A A (low ) E E (low) B B High Z When not Enabled (E = ) the three state buffer acts lika a huge resistance, kind of cutting of the wire We cannot have high and low voltage at the same time (high) (low) (high) (low) (high) (high) High Z (low) (high) When Enabled (E = ) the three state buffer lets the input signal A through E = Error Output B can be in three states, (low), (high) and high resistance (Z) A three state buffer acts like a true switch compared to a transistor A multilexor an use three state buffers to implement a multiplexor A tranistor is never completely off, only the number of electrons used to form the current can be controlled high or low current A shared data line (bus) 4x2 AM Memory A Flip-Flop Using three state buffer instead of multiplerxors make it possible to share data lines 4x4 AM Memory Using three state buffer instead of multiplerxors make it easy to extend A shared output data bus Address line, aka word line 4x8 bit = = Word 7

8 tatic andom Access Memory 4x4 AM Memory andom? andom: takes the same time to access any random memory location tatic? En kondensator (apacitor) är som en läckande hink med vatten Kondensatorn fylls på med elektroner och laddas därmed upp Efter en tid "rinner" ellektronerna ut och kondensatorn tappar sin laddning Hmm, en kondensator borde kunna användas för att lagra en bit ynd bara att den tappar sitt minne efter ett tag Write: assert word line, drive new value on bit line Word Line Word Line apacitor ead: assert word line, sense value on bit line (destroys saved value) Bit Line Asserting both the Word Line and the Bit Line charges the capacitor Bit Line eading a bit destroys the bit must refresh the memory cell bit line Word Lines Bit ell word line ince real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically High Low Bit Lines ense Amplifier A latch is used to remember a whole word line because of this refresh requirement, it is a dynamic random access memory as opposed to AM and other static memory Address ata AM 8

9 AM AM Normal AM drives many bits (row) out of array, selects few to output Latch Adding latch at row outputs allows us to save an entire row of the AM Later accesses to the AM can eliminate the row access time, just need column access time Most common in AM, page-mode AMs also exist Faster table - holds value as long as power applied Less dense (4-6 transistors/bit) More expensive per bit Unstable - needs refresh lower High density ( ransistor/bit) Less expensive per bit egisters must be as fast as possible, hence Flip-Flop memory similar to AM is used for registers ince we use quite a few registers, the low bit denisity does not matter that much 9

Relevanta dokument

Datorarkitektur 1. Sekventiella kretsar (minne) December 2008

Datorarkitektur 1. Sekventiella kretsar (minne) December 2008 Datorarkitektur Sekventiella kretsar (minne) December 28 karl.marklund@it.uu.se B M C A The function can be described by a thruth table. 4 Minterms The majority function Tools such as Logisim can calculate