Sekventiella krestar (minne) Datorarkitektur 1 (1DT038) Föreläsning 6 Tisdag 16 November 2009 karl.marklund@it.uu.se
4 Minterms The majority function A B C M 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 The function can be described using a thruth table. 1 0 1 1 1 1 0 1 1 1 1 1
Tools such as Logisim can calculate the thruth table from a circuit...and minimize the expression using a Karnaugh map......and build the minimized circuit for us!
You can also specify inputs and outputs as a truth table in Logisim...
Minimize the expression......or even build the circuit.
För en kombinatorisk krets gäller att det existerar en entydig kombination av utsignal-tillstånd för varje möjlig kombination av insignaler. En utsignal från en kombinatorisk krets beror ej av kretsens historia dvs tidigare in-signalvärden - kretsen saknar minne! Är detta en kombinatorisk krets? Därför kan kombinatoriska logiska kretsars funktion beskrivas med hjälp av sanningstabeller. register a 5 bit register b 5 bit Registers 32 bit Vi har sett att vi kan konstruera en ALU med 32 bit hjälp av kombinatoriska kretstar. ALU OP register c 5 bit 32 bit
Om det var en kombinatorisk krets skulle vi få samma utdata för samma indata varje gång register a 5 bit 32 bit register b 5 bit 32 Registers 32 bit En kombinatorisk krets kan inte ha feedback (återkoppling). ALU OP register c 5 bit 32 bit och vad är nu det här? På en och samma adress vill vi kunna lagra olika data vid olika tillfällen.
Vi behöver krestar med minne.
An example of sequential logic: The output depends not only on the present input but also on the history of the input. R S Q n+1 Q n+1 0 0 Q n Q n 0 1 1 0 1 0 0 1 1 1 Restricted A couple of cross coupled nor-gates can be used to store one bit of information. If both R and S drops to zero at the same time metastability
R S Q Q A latch is a sequential device that watches all of its inputs continuously and changes its outputs at any time. SR Latch R S Q n+1 Q n+1 0 0 Q n Q n 0 1 1 0 1 0 0 1 1 1 Restricted A flip-flop is a sequential device that samples its inputs and changes its outputs only at times determined by a clocking signal. C D Q Q D Latch / Flip-Flop C D Q n+1 Q n+1 Comment 0 X Q n Q n No Change 1 0 0 1 Reset 1 1 1 0 Set
The triangle indicates an edge-trigged latch a flip flop. C Q A D Flip-Flop The inversion bubble on the clock input indicate a falling-edge triggered flip-flop D Q C D Q n+1 Q n+1 Comment non-falling X Q n Q n No Change 1 1 0 Set 0 0 1 Reset
Vill du veta mer om hur det går till att konstruera olika typer av vippor och latchar med hjälp av enkla grindar? I så fall kan du läsa mer om detta i denna fördjupning.
A register is a component that can be used to store integers (bit patterns). 8 bit data input, a number we want to store and remember. 8 bit register Value of stored number in hexadecimal notation. 8 bit data output, value of stored number. 1 bit clear input used to reset stored value to zero. To change the state (contents) of the register, the value on this 1 bit input must change from low (0) to high (1), i.e., a rasing edge trigged state element.
Vi börjar med 8 stycken register om 8 bitar var.
Vi vill kunna nollställa alla register.
Vi vill kunna lagra tal (8 bitar) i de olika registren.
Eftersom registren är kant-triggade lägger vi till en klocksignal.
För att kunna välja ut vilket register vi vill uppdatera lägger vi till en demultiplexer.
För att välja ett register att läsa från lägger vi till en multiplexer.
För att kunna läsa ut data från två register lägger vi till ytterligare en multiplexer.
We have now built a complete register file. register a 3 bit register b 3 bit Registers 8 bit 8 bit ALU OP register c 3 bit 8 bit
Varje cell har en unik adress. Fyra bytes bildar ett ord (word) om 32 bitar. MEMORY Address Content 0xFFFFFFFF 0xFFFFFFFE 0xFFFFFFFD 0xFFFFFFFC... 0x00000003 0x00000002 0x00000001 0x00000000 I MIPS består minnet av 2 32 celler. Varje cell i minnet kan lagra åtta bitar, dvs en byte. Kan vi bygga minnet på samma sätt som registerfilen?
32 stycken 2 32 stycken MEMORY Address Content 0xFFFFFFFF 0xFFFFFFFE 0xFFFFFFFD 0xFFFFFFFC... 0x00000003 0x00000002 0x00000001 0x00000000 Giant Multiplexor
Möjligt, men absolut inte praktiskt att bygga ut till 2 32 olika data inputs......och 32 select input.
All inputs share the same output line. What happens if we change to 1 here? Signals are not 1 or 0... Signals on the wire are high or low voltage. We cannot have high and low voltage at the same time. E = Error
Three State Buffer A B C 0 (low ) 0 (low) High Z When not Enabled (B = 0) the three state buffer acts like a huge resistance, kind of cutting of the wire. 1 (high) 0 (low) High Z 0 (low) 1 (high) 0 (low) 1 (high) 1 (high) 1 (high) When Enabled (B = 1) the three state buffer lets the input signal A through. Output C can be in three states, 0 (low), 1 (high) and high resistance (Z).
A tranistor is never completely off, only the number of electrons used to form the current can be controlled high or low current A three state buffer acts like a true switch compared to a transistor.
A multiplexor implementation...... another multiplexor implementation... A shared data line (data bus) What is the benefit of using three state buffers instead of a multiplexor?
4x2 SRAM Memory A D Flip-Flop Using three state buffers instead of multiplerxors make it possible to share data lines. Using a 2-bit address, we select one of the four data rows (16 bit of data) A shared output data bus.
4x4 SRAM Memory Using three state buffers instead of multiplerxors makes it easy to extend... Address line, aka word line. 4x8 bit = 32 bit = 1 Word
Static Random Access Memory 4x4 SRAM Memory Random? Random: takes the same time to access any random memory location. Static?
En kondensator (Capacitor) är som en läckande hink med vatten. Kondensatorn fylls på med elektroner och laddas därmed upp. Efter en tid "rinner" ellektronerna ut och kondensatorn tappar sin laddning. Hmm, en kondensator borde kunna användas för att lagra en bit... Synd bara att den tappar sitt minne efter ett tag...
Transistor Capacitor Asserting both the Word Line and the Bit Line charges the capacitor
Write: assert word line, drive new value (0/1) on bit line. Read: assert word line, sense value on bit line (destroys saved value) Reading a bit destroys the bit must refresh the memory cell.
bit line word line Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically A latch is used to remember all 4 bits from the selected word line because of this refresh requirement, it is a dynamic random access memory as opposed to SRAM and other types of static DRAM a0, a1 anger rad a2, a3 anger kolumn
Normal RAM drives many bits (row) out of array, selects few to output. Adding latch at row outputs allows us to save an entire row of the RAM Later accesses to the RAM can eliminate the row access time, just need column access time Most common in DRAM, page-mode SRAMs also exist
SRAM DRAM Stable - holds value as long as power applied Faster Less dense (4-6 transistors/bit) More expensive per bit Unstable - needs refresh Slower High density (1 transistor/bit) Less expensive per bit Which of the above technologies would you choose for the register file? Motivate your choise?
SRAM DRAM Stable - holds value as long as power applied Faster Less dense (4-6 transistors/bit) More expensive per bit Unstable - needs refresh Slower High density (1 ransistor/bit) Less expensive per bit Registers must be as fast as possible, hence Flip-Flop memory similar to SRAM is used for registers. Since we use quite a few registers, the low bit denisity does not matter that much.
John Von Neumann, who lived from 1903-1957, was working at the Institute for Advanced Study when he became fascinated by the success of the ENIAC. This fascination would lead him to undertake an abstract study of computation that showed that: a computer should have a very simple, fixed physical structure, and yet be able to execute any kind of computation by means of a proper programmed control without the need for any change in the unit itself.
John von Neuman 1945: The stored program computer The von Neuman model
Ur den formella kursplanen: Efter genomgången kurs skall deltagarna ingående kunna beskriva funktionen hos och uppbyggnaden av en dators delar såsom -styrenhet - primärminne - in- och utmatningssystem Nu har vi lagt grunden och kan börja kika närmare på dessa bitar. Deltagarna skall kunna programmera i assemblerspråk.
Jaha... Men enligt den informella kursplanen då? Hur kul som hellst! Vi får lära oss från grunden hur en dator egentligen fungerar. När jag gått kursen kan jag i princip springa ner på stan och köpa en säck transistorer, bygga en dator och programmera den.