Freescale MC9S12DG256B

2011 10 11 Freescale MC9S12DG256B Uppbyggnad och enheter Minnen MC9S12DG256B Processorkärna Portar VR [40] VREGEN [97] V1 [14] V2 [66] MODC/TGHI/BKGD [23] XFC [44] VPLL [45] EXTL [46] XTL [47] RESET [42] XIRQ PE0 [56] IRQ PE1 [55] R/W PE2 [54] LSTRB/TG0 PE3 [53] ECLK PE4 [39] MOD/IPIPE0 PE5 [38] MODB/IPIPE1 PE6 [37] NOCC/XCLKS PE7 [36] TEST [48] PTE DDRE 256K Byte Flash EEPROM 12K Byte RM 4K Byte EEPROM Voltage Regulator Single-wire Background Debug Module CPU12 Clock and PLL Reset Periodic Interrupt Generation COP Watchdog Module Clock Monitor Breakpoints XIRQ IRQ R/W System LSTRB Integration ECLK Module (SIM) MOD MODB NOCC/XCLKS ddress/data Bus DDR DDRB PT PTB P7 [64] P6 [63] P5 [62] P4 [61] P3 [60] P2 [59] P1 [58] P0 [57] PB7 [31] PB6 [30] PB5 [29] PB4 [28] PB3 [27] PB2 [26] PB1 [25] PB0 [24] DDR15 DDR14 DDR13 DDR12 DDR11 DDR10 DDR9 DDR8 DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 TD0 VRL VDD V N0 N1 N2 N3 N4 N5 N6 N7 D0 SCI0 SCI1 SPI0 CN0 CN4 PD00 [67] PD01 [69] PD02 [71] PD03 [73] PD04 [75] PD05 [77] PD06 [79] PD07/ETRIG0 [81] PPGE Enhanced Capture Timer RXCN TXCN RXCN TXCN Module to Port Routing PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 TD1 VRL VDD V N8 N9 N10 N11 N12 N13 N14 N15 DDRM DDRS DDRT DDRK PTM PTS PTT PTK D1 [84] VRL [85] VDD [83] V [86] PD08 [68] PD09 [70] PD10 [72] PD11 [74] PD12 [76] PD13 [78] PD14 [80] PD15/ETRIG1 [82] PK0 [8] XDDR14 PK1 [7] XDDR15 PK2 [6] XDDR16 PK3 [5] XDDR17 PK4 [20] XDDR18 PK5 [19] XDDR19 PK7 [108] ECS/ROMCTL PT0 [9] IOC0 PT1 [10] IOC1 PT2 [11] IOC2 PT3 [12] IOC3 PT4 [15] IOC4 PT5 [16] IOC5 PT6 [17] IOC6 PT7 [18] IOC7 PS0 [89] 0 PS1 [90] 0 PS2 [91] 1 PS3 [92] 1 PS4 [93] 0 PS5 [94] M0SI0 PS6 [95] 0 PS7 [96] 0 PM0 [105] RXCN0 PM1 [104] TXCN0 PM2 [103] RXCN0 0 PM3 [102] TXCN0 0 PM4 [101] RXCN0 RXCN4 M0SI0 PM5 [100] TXCN0 TXCN4 0 PM6 [88] RXCN4 PM7 [87] TXCN4 Periferienheter Kontroll av pagat minne Portar Wide Bus DT15 DT14 DT13 DT12 DT11 DT10 DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 IIC SD SCL KWJ0 KWJ1 KWJ6 KWJ7 DDRJ PTJ PJ0 [22] PJ1 [21] PJ6 [99] PJ7 [98] RXCN0 RXCN4 SD TXCN0 TXCN4 SCL Portar för externt minne Narrow Bus DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Internal Logic 2.5V I/O Driver 5V VDDx [107] V1 [14] Vx [106] V2 [66] /D Converter 5V & PLL 2.5V Voltage Regulator Reference VDD [83] VPLL [45] V [86] PWM0 PWM1 PWM2 PWM3 PWM PWM4 PWM5 PWM6 PWM7 SPI1 SPI2 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 DDRH DDRP PTH PTP PP0 [4] PWM0 1 PP1 [3] PWM1 M0SI1 PP2 [2] PWM2 1 PP3 [1] PWM3 1 PP4 [112] PWM4 2 PP5 [111] PWM5 M0SI2 PP6 [110] PWM6 2 PP7 [109] PWM7 2 PH0 [52] 1 PH1 [51] M0SI1 PH2 [50] 1 PH3 [49] 1 PH4 [35] 2 PH5 [34] M0SI2 PH6 [33] 2 PH7 [32] 2 Voltage Regulator 5V & I/O VR [40] 1

2011 10 11 Klockor och faslåst loop (PLL) Processorkärna BDM Centralenhet Klockkristall Extern reset Externa interrupt Läs/skriv E klocka Konfigureringsben Data/adressbuss Minnen MC9S12DG256B VR [40] VREGEN [97] V1 [14] V2 [66] 256K Byte Flash EEPROM 12K Byte RM 4K Byte EEPROM Voltage Regulator TD0 VRL VDD V N0 N1 N2 N3 N4 N5 N6 N7 D0 PD00 [67] PD01 [69] PD02 [71] PD03 [73] PD04 [75] PD05 [77] PD06 [79] PD07/ETRIG0 [81] TD1 VRL VDD V N8 N9 N10 N11 N12 N13 N14 N15 D1 [84] VRL [85] VDD [83] V [86] PD08 [68] PD09 [70] PD10 [72] PD11 [74] PD12 [76] PD13 [78] PD14 [80] PD15/ETRIG1 [82] Single-wire Background MODC/TGHI/BKGD [23] Debug Module XFC [44] Clock and VPLL [45] PLL Reset EXTL [46] Generation XTL [47] Module RESET [42] XIRQ PE0 [56] IRQ PE1 [55] R/W PE2 [54] LSTRB/TG0 PE3 [53] ECLK PE4 [39] MOD/IPIPE0 PE5 [38] MODB/IPIPE1 PE6 [37] NOCC/XCLKS PE7 [36] TEST [48] P7 [64] PTE P6 [63] DDRE P5 [62] P4 [61] P3 [60] P2 [59] P1 [58] P0 [57] ddress/data Bus DDR PT XIRQ IRQ R/W LSTRB ECLK MOD MODB NOCC/XCLKS DDR15 DDR14 DDR13 DDR12 DDR11 DDR10 DDR9 DDR8 CPU12 Periodic Interrupt COP Watchdog Clock Monitor Breakpoints System Integration Module (SIM) DDRB PTB PB7 [31] PB6 [30] PB5 [29] PB4 [28] PB3 [27] PB2 [26] PB1 [25] PB0 [24] DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 PPGE Enhanced Capture Timer SCI0 SCI1 SPI0 RXCN CN0 TXCN RXCN CN4 TXCN Module to Port Routing PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 DDRM DDRS DDRT DDRK PTM PTS PTT PTK PK0 [8] XDDR14 PK1 [7] XDDR15 PK2 [6] XDDR16 PK3 [5] XDDR17 PK4 [20] XDDR18 PK5 [19] XDDR19 PK7 [108] ECS/ROMCTL PT0 [9] IOC0 PT1 [10] IOC1 PT2 [11] IOC2 PT3 [12] IOC3 PT4 [15] IOC4 PT5 [16] IOC5 PT6 [17] IOC6 PT7 [18] IOC7 PS0 [89] 0 PS1 [90] 0 PS2 [91] 1 PS3 [92] 1 PS4 [93] 0 PS5 [94] M0SI0 PS6 [95] 0 PS7 [96] 0 PM0 [105] RXCN0 PM1 [104] TXCN0 PM2 [103] RXCN0 0 PM3 [102] TXCN0 0 PM4 [101] RXCN0 RXCN4 M0SI0 PM5 [100] TXCN0 TXCN4 0 PM6 [88] RXCN4 PM7 [87] TXCN4 Wide Bus DT15 DT14 DT13 DT12 DT11 DT10 DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 IIC SD SCL KWJ0 KWJ1 KWJ6 KWJ7 DDRJ PTJ PJ0 [22] PJ1 [21] PJ6 [99] PJ7 [98] RXCN0 RXCN4 SD TXCN0 TXCN4 SCL Narrow Bus DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Internal Logic 2.5V I/O Driver 5V VDDx [107] V1 [14] Vx [106] PWM PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 DDRP PTP PP0 [4] PWM0 1 PP1 [3] PWM1 M0SI1 PP2 [2] PWM2 1 PP3 [1] PWM3 1 PP4 [112] PWM4 2 PP5 [111] PWM5 M0SI2 PP6 [110] PWM6 2 PP7 [109] PWM7 2 V2 [66] PLL 2.5V VPLL [45] /D Converter 5V & Voltage Regulator Reference VDD [83] V [86] SPI1 SPI2 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 DDRH PTH PH0 [52] 1 PH1 [51] M0SI1 PH2 [50] 1 PH3 [49] 1 PH4 [35] 2 PH5 [34] M0SI2 PH6 [33] 2 PH7 [32] 2 Voltage Regulator 5V & I/O VR [40] 2

Minnen 16 sidor om 16K, 2 fasta 14 pagade Flyktigt minne, bland annat registerarea Flashminne kan bara hanteras (skrivas och raderas) i block EEPROM kan hanteras adress för adress Minneskarta 3

2011 10 11 MC9S12DG256B VR [40] VREGEN [97] V1 [14] V2 [66] 256K Byte Flash EEPROM 12K Byte RM 4K Byte EEPROM Voltage Regulator TD0 VRL VDD V N0 N1 N2 N3 N4 N5 N6 N7 D0 PD00 [67] PD01 [69] PD02 [71] PD03 [73] PD04 [75] PD05 [77] PD06 [79] PD07/ETRIG0 [81] TD1 VRL VDD V N8 N9 N10 N11 N12 N13 N14 N15 D1 [84] VRL [85] VDD [83] V [86] PD08 [68] PD09 [70] PD10 [72] PD11 [74] PD12 [76] PD13 [78] PD14 [80] PD15/ETRIG1 [82] Single-wire Background MODC/TGHI/BKGD [23] Debug Module XFC [44] Clock and VPLL [45] PLL Reset EXTL [46] Generation XTL [47] Module RESET [42] XIRQ PE0 [56] IRQ PE1 [55] R/W PE2 [54] LSTRB/TG0 PE3 [53] ECLK PE4 [39] MOD/IPIPE0 PE5 [38] MODB/IPIPE1 PE6 [37] NOCC/XCLKS PE7 [36] TEST [48] P7 [64] PTE P6 [63] DDRE P5 [62] P4 [61] P3 [60] P2 [59] P1 [58] P0 [57] ddress/data Bus DDR PT XIRQ IRQ R/W LSTRB ECLK MOD MODB NOCC/XCLKS DDR15 DDR14 DDR13 DDR12 DDR11 DDR10 DDR9 DDR8 CPU12 Periodic Interrupt COP Watchdog Clock Monitor Breakpoints System Integration Module (SIM) DDRB PTB PB7 [31] PB6 [30] PB5 [29] PB4 [28] PB3 [27] PB2 [26] PB1 [25] PB0 [24] DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 PPGE Enhanced Capture Timer SCI0 SCI1 SPI0 RXCN CN0 TXCN RXCN CN4 TXCN Module to Port Routing PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 DDRM DDRS DDRT DDRK PTM PTS PTT PTK PK0 [8] XDDR14 PK1 [7] XDDR15 PK2 [6] XDDR16 PK3 [5] XDDR17 PK4 [20] XDDR18 PK5 [19] XDDR19 PK7 [108] ECS/ROMCTL PT0 [9] IOC0 PT1 [10] IOC1 PT2 [11] IOC2 PT3 [12] IOC3 PT4 [15] IOC4 PT5 [16] IOC5 PT6 [17] IOC6 PT7 [18] IOC7 PS0 [89] 0 PS1 [90] 0 PS2 [91] 1 PS3 [92] 1 PS4 [93] 0 PS5 [94] M0SI0 PS6 [95] 0 PS7 [96] 0 PM0 [105] RXCN0 PM1 [104] TXCN0 PM2 [103] RXCN0 0 PM3 [102] TXCN0 0 PM4 [101] RXCN0 RXCN4 M0SI0 PM5 [100] TXCN0 TXCN4 0 PM6 [88] RXCN4 PM7 [87] TXCN4 Wide Bus DT15 DT14 DT13 DT12 DT11 DT10 DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 IIC SD SCL KWJ0 KWJ1 KWJ6 KWJ7 DDRJ PTJ PJ0 [22] PJ1 [21] PJ6 [99] PJ7 [98] RXCN0 RXCN4 SD TXCN0 TXCN4 SCL Portar för externt minne Narrow Bus DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Internal Logic 2.5V I/O Driver 5V VDDx [107] V1 [14] Vx [106] V2 [66] /D Converter 5V & PLL 2.5V Voltage Regulator Reference VDD [83] VPLL [45] V [86] PWM0 PWM1 PWM2 PWM3 PWM PWM4 PWM5 PWM6 PWM7 SPI1 SPI2 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 DDRH DDRP PTH PTP PP0 [4] PWM0 1 PP1 [3] PWM1 M0SI1 PP2 [2] PWM2 1 PP3 [1] PWM3 1 PP4 [112] PWM4 2 PP5 [111] PWM5 M0SI2 PP6 [110] PWM6 2 PP7 [109] PWM7 2 PH0 [52] 1 PH1 [51] M0SI1 PH2 [50] 1 PH3 [49] 1 PH4 [35] 2 PH5 [34] M0SI2 PH6 [33] 2 PH7 [32] 2 Voltage Regulator 5V & I/O VR [40] Externt minne Läs/skriv Styr MUX av adress/data 16 adressledningar 16 dataledningar i wide mode dress och data är multiplexade 8 dataledningar i narrow mode 4

Tidsförlopp för access av externt minne Läs adress Läs/skriv data Lägg ut adress på buss Lägg ut data på buss Kontroll av externt minne 32K 32k=2 15 15 adressledningar Minnet aktiveras då 15=1 Läs minne Skriv minne 5

2011 10 11 MC9S12DG256B VR [40] VREGEN [97] V1 [14] V2 [66] MODC/TGHI/BKGD [23] XFC [44] VPLL [45] EXTL [46] XTL [47] RESET [42] XIRQ PE0 [56] IRQ PE1 [55] R/W PE2 [54] LSTRB/TG0 PE3 [53] ECLK PE4 [39] MOD/IPIPE0 PE5 [38] MODB/IPIPE1 PE6 [37] NOCC/XCLKS PE7 [36] TEST [48] PTE DDRE 256K Byte Flash EEPROM 12K Byte RM 4K Byte EEPROM Voltage Regulator Single-wire Background Debug Module CPU12 Clock and PLL Reset Periodic Interrupt Generation COP Watchdog Module Clock Monitor Breakpoints XIRQ IRQ R/W System LSTRB Integration ECLK Module (SIM) MOD MODB NOCC/XCLKS ddress/data Bus DDR DDRB PT PTB P7 [64] P6 [63] P5 [62] P4 [61] P3 [60] P2 [59] P1 [58] P0 [57] PB7 [31] PB6 [30] PB5 [29] PB4 [28] PB3 [27] PB2 [26] PB1 [25] PB0 [24] DDR15 DDR14 DDR13 DDR12 DDR11 DDR10 DDR9 DDR8 DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 TD0 VRL VDD V N0 N1 N2 N3 N4 N5 N6 N7 D0 SCI0 SCI1 SPI0 CN0 CN4 PD00 [67] PD01 [69] PD02 [71] PD03 [73] PD04 [75] PD05 [77] PD06 [79] PD07/ETRIG0 [81] PPGE Enhanced Capture Timer RXCN TXCN RXCN TXCN Module to Port Routing PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 TD1 VRL VDD V N8 N9 N10 N11 N12 N13 N14 N15 DDRM DDRS DDRT DDRK PTM PTS PTT PTK D1 [84] VRL [85] VDD [83] V [86] PD08 [68] PD09 [70] PD10 [72] PD11 [74] PD12 [76] PD13 [78] PD14 [80] PD15/ETRIG1 [82] PK0 [8] XDDR14 PK1 [7] XDDR15 PK2 [6] XDDR16 PK3 [5] XDDR17 PK4 [20] XDDR18 PK5 [19] XDDR19 PK7 [108] ECS/ROMCTL PT0 [9] IOC0 PT1 [10] IOC1 PT2 [11] IOC2 PT3 [12] IOC3 PT4 [15] IOC4 PT5 [16] IOC5 PT6 [17] IOC6 PT7 [18] IOC7 PS0 [89] 0 PS1 [90] 0 PS2 [91] 1 PS3 [92] 1 PS4 [93] 0 PS5 [94] M0SI0 PS6 [95] 0 PS7 [96] 0 PM0 [105] RXCN0 PM1 [104] TXCN0 PM2 [103] RXCN0 0 PM3 [102] TXCN0 0 PM4 [101] RXCN0 RXCN4 M0SI0 PM5 [100] TXCN0 TXCN4 0 PM6 [88] RXCN4 PM7 [87] TXCN4 Periferienheter Wide Bus DT15 DT14 DT13 DT12 DT11 DT10 DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 IIC SD SCL KWJ0 KWJ1 KWJ6 KWJ7 DDRJ PTJ PJ0 [22] PJ1 [21] PJ6 [99] PJ7 [98] RXCN0 RXCN4 SD TXCN0 TXCN4 SCL Narrow Bus DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Internal Logic 2.5V I/O Driver 5V VDDx [107] V1 [14] Vx [106] PWM PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 DDRP PTP PP0 [4] PWM0 1 PP1 [3] PWM1 M0SI1 PP2 [2] PWM2 1 PP3 [1] PWM3 1 PP4 [112] PWM4 2 PP5 [111] PWM5 M0SI2 PP6 [110] PWM6 2 PP7 [109] PWM7 2 V2 [66] PLL 2.5V VPLL [45] /D Converter 5V & Voltage Regulator Reference VDD [83] V [86] SPI1 SPI2 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 DDRH PTH PH0 [52] 1 PH1 [51] M0SI1 PH2 [50] 1 PH3 [49] 1 PH4 [35] 2 PH5 [34] M0SI2 PH6 [33] 2 PH7 [32] 2 Voltage Regulator 5V & I/O VR [40] Periferienheter Två 8 kanalers DC MUX:ade ingångar Timer Två asynkrona serieportar (SCI) nvänds inte en enhet så kan porten användas som allmän in/utport D bara inport OBS kan placeras på olika portar Två CN interface I 2 C buss interface 8 kanaler PWM Tre synkrona serieportar (SPI) 6

D omvandlare Två D omvandlare med 8 multiplexade kanaler dvs dsbara a en kanal a per omvandlare samtidigt 8 eller 10 bitar 7 µs omvandlingstid/kanal dvs max samplingsfrekvens 1/ 7 µs 140 khz vid en kanal 140/8 = 17,8 khz vid åtta kanaler Timer 16 bitars räknare 16 bitars modulo nedräknare med 4 bitars prescaler Kortaste tid: 1 klockpuls 1/8 MHz = 125 ns Längsta tid: 2 4 *2 16 klockpulser = 1 048 576*125 ns ~ 131 ms Prescaler Modulo nedräknare Fyra 8 bitars pulsräknare som kan användas som två 16 bitars pulsräknare Flexibla avbrottsfunktioner Åtta 16 bitars register för input capture och output compare 7

Timer forts Input capture används för att vid ett triggvillkor lagra räknarens nuvarande värde Output compare används för att ge signal eller avbrott då räknaren har nått ett visst värde Tillsammans kan de användas för timingfunktioner Läs räknaren via input capture Lägg på en offset till värdet Lagra värdet i output compare register Vänta till dess räknaren har detta värde Output compare signalerar t ex via avbrott synkron serieport (SCI) Två vanliga serieportar I enklaste form (som här) bara en sändledning (Tx) och en mottagningsledning (Rx) samt jord nvänder en konfigurerbar överföringshastighet (Baudrate) typiskt 9,6 115,2 kbaud Inga speciella synkroniseringssignaler Synkronisering via start och stoppbitar i dataflödet Svag synkronisering ger låg överföringshastighet 8

Synkron serieport (SPI) Tre synkrona serieportar Master/slave protokoll styrt av mastern Fyra yasg signaler ae Därav två signaler för data Master Out Slave In Master In Slave Out och två signaler för synkronisering SCLK serieklocka slave select Snabbare än SCI pga synkroniseringen, upp till 10 MHz CN interface Bussinterface, alla enheter kan sända och ta emot meddelanden Balanserad tvåtrådsbuss via extern CN driver Normalhastighet 1 Mbps Max 8 byte data per meddelande Meddelandebaserat Varje meddelande innehåller en 11 eller 29 bitars identifierare Enheter är konfigurerade för att ta emot och sända meddelanden med en eller flera av dessa identifierare Flera mottagare kan ta emot samma meddelande Sändare och mottagare har alltså inga egna adresser CN har förmåga att upptäcka om flera enheter försöker sända samtidigt på bussen Identifieraren ger prioritet till meddelandet och sändare med meddelanden av lägre prioritet avbryter sändningen för att försöka sända lite senare 9

I2C buss Bussinterface med en master och en eller flera slavar ll kommunikation initieras av mastern Slavarnasvarar påanropfrånmastern Två ledningar Databussledning Serieklockledning Tre hastigheter slow, 100 Kbps fast, 400 Kbps high speed, 3,4 Mbps Åtta kanaler Pulsbreddsmodulering (PWM) nvänds för styrning En form av D/ omvandling Hos en signal med konstant frekvens varieras pulskvoten Pulskvot = Tid för etta/periodtid*100% Högre pulskvot motsvarar högre signalvärde Via lågpassfiltrering av signalen kan pulsen elimineras och vi får en analog signal som varierar i storlek i takt med pulskvoten nvänds bl a i klass D förstärkare digital förstärkare 10

2011 10 11 Pulsbreddsmodulering (PWM) forts. MC9S12DG256B VR [40] VREGEN [97] V1 [14] V2 [66] 256K Byte Flash EEPROM 12K Byte RM 4K Byte EEPROM Voltage Regulator TD0 VRL VDD V N0 N1 N2 N3 N4 N5 N6 N7 D0 PD00 [67] PD01 [69] PD02 [71] PD03 [73] PD04 [75] PD05 [77] PD06 [79] PD07/ETRIG0 [81] TD1 VRL VDD V N8 N9 N10 N11 N12 N13 N14 N15 D1 [84] VRL [85] VDD [83] V [86] PD08 [68] PD09 [70] PD10 [72] PD11 [74] PD12 [76] PD13 [78] PD14 [80] PD15/ETRIG1 [82] Portar Single-wire Background MODC/TGHI/BKGD [23] Debug Module XFC [44] Clock and VPLL [45] PLL Reset EXTL [46] Generation XTL [47] Module RESET [42] XIRQ PE0 [56] IRQ PE1 [55] R/W PE2 [54] LSTRB/TG0 PE3 [53] ECLK PE4 [39] MOD/IPIPE0 PE5 [38] MODB/IPIPE1 PE6 [37] NOCC/XCLKS PE7 [36] TEST [48] P7 [64] PTE P6 [63] DDRE P5 [62] P4 [61] P3 [60] P2 [59] P1 [58] P0 [57] ddress/data Bus DDR PT XIRQ IRQ R/W LSTRB ECLK MOD MODB NOCC/XCLKS DDR15 DDR14 DDR13 DDR12 DDR11 DDR10 DDR9 DDR8 CPU12 Periodic Interrupt COP Watchdog Clock Monitor Breakpoints System Integration Module (SIM) DDRB PTB PB7 [31] PB6 [30] PB5 [29] PB4 [28] PB3 [27] PB2 [26] PB1 [25] PB0 [24] DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 PPGE Enhanced Capture Timer SCI0 SCI1 SPI0 RXCN CN0 TXCN RXCN CN4 TXCN Module to Port Routing PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 DDRM DDRS DDRT DDRK PTM PTS PTT PTK PK0 [8] XDDR14 PK1 [7] XDDR15 PK2 [6] XDDR16 PK3 [5] XDDR17 PK4 [20] XDDR18 PK5 [19] XDDR19 PK7 [108] ECS/ROMCTL PT0 [9] IOC0 PT1 [10] IOC1 PT2 [11] IOC2 PT3 [12] IOC3 PT4 [15] IOC4 PT5 [16] IOC5 PT6 [17] IOC6 PT7 [18] IOC7 PS0 [89] 0 PS1 [90] 0 PS2 [91] 1 PS3 [92] 1 PS4 [93] 0 PS5 [94] M0SI0 PS6 [95] 0 PS7 [96] 0 PM0 [105] RXCN0 PM1 [104] TXCN0 PM2 [103] RXCN0 0 PM3 [102] TXCN0 0 PM4 [101] RXCN0 RXCN4 M0SI0 PM5 [100] TXCN0 TXCN4 0 PM6 [88] RXCN4 PM7 [87] TXCN4 Portar Wide Bus DT15 DT14 DT13 DT12 DT11 DT10 DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 IIC SD SCL KWJ0 KWJ1 KWJ6 KWJ7 DDRJ PTJ PJ0 [22] PJ1 [21] PJ6 [99] PJ7 [98] RXCN0 RXCN4 SD TXCN0 TXCN4 SCL Narrow Bus DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Internal Logic 2.5V I/O Driver 5V VDDx [107] V1 [14] Vx [106] PWM PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 DDRP PTP PP0 [4] PWM0 1 PP1 [3] PWM1 M0SI1 PP2 [2] PWM2 1 PP3 [1] PWM3 1 PP4 [112] PWM4 2 PP5 [111] PWM5 M0SI2 PP6 [110] PWM6 2 PP7 [109] PWM7 2 V2 [66] PLL 2.5V VPLL [45] /D Converter 5V & Voltage Regulator Reference VDD [83] V [86] SPI1 SPI2 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 DDRH PTH PH0 [52] 1 PH1 [51] M0SI1 PH2 [50] 1 PH3 [49] 1 PH4 [35] 2 PH5 [34] M0SI2 PH6 [33] 2 PH7 [32] 2 Voltage Regulator 5V & I/O VR [40] 11

2011 10 11 Portar Inportar lternativa användningar Inte komplett port In /utportar In /utport eller periferienhet MC9S12DG256B VR [40] VREGEN [97] V1 [14] V2 [66] 256K Byte Flash EEPROM 12K Byte RM 4K Byte EEPROM Voltage Regulator TD0 VRL VDD V N0 N1 N2 N3 N4 N5 N6 N7 D0 PD00 [67] PD01 [69] PD02 [71] PD03 [73] PD04 [75] PD05 [77] PD06 [79] PD07/ETRIG0 [81] TD1 VRL VDD V N8 N9 N10 N11 N12 N13 N14 N15 D1 [84] VRL [85] VDD [83] V [86] PD08 [68] PD09 [70] PD10 [72] PD11 [74] PD12 [76] PD13 [78] PD14 [80] PD15/ETRIG1 [82] Single-wire Background MODC/TGHI/BKGD [23] Debug Module XFC [44] Clock and VPLL [45] PLL Reset EXTL [46] Generation XTL [47] Module RESET [42] XIRQ PE0 [56] IRQ PE1 [55] R/W PE2 [54] LSTRB/TG0 PE3 [53] ECLK PE4 [39] MOD/IPIPE0 PE5 [38] MODB/IPIPE1 PE6 [37] NOCC/XCLKS PE7 [36] TEST [48] P7 [64] PTE P6 [63] DDRE P5 [62] P4 [61] P3 [60] P2 [59] P1 [58] P0 [57] ddress/data Bus DDR PT XIRQ IRQ R/W LSTRB ECLK MOD MODB NOCC/XCLKS DDR15 DDR14 DDR13 DDR12 DDR11 DDR10 DDR9 DDR8 CPU12 Periodic Interrupt COP Watchdog Clock Monitor Breakpoints System Integration Module (SIM) DDRB PTB PB7 [31] PB6 [30] PB5 [29] PB4 [28] PB3 [27] PB2 [26] PB1 [25] PB0 [24] DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 PPGE Enhanced Capture Timer SCI0 SCI1 SPI0 RXCN CN0 TXCN RXCN CN4 TXCN Module to Port Routing PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 DDRM DDRS DDRT DDRK PTM PTS PTT PTK PK0 [8] XDDR14 PK1 [7] XDDR15 PK2 [6] XDDR16 PK3 [5] XDDR17 PK4 [20] XDDR18 PK5 [19] XDDR19 PK7 [108] ECS/ROMCTL PT0 [9] IOC0 PT1 [10] IOC1 PT2 [11] IOC2 PT3 [12] IOC3 PT4 [15] IOC4 PT5 [16] IOC5 PT6 [17] IOC6 PT7 [18] IOC7 PS0 [89] 0 PS1 [90] 0 PS2 [91] 1 PS3 [92] 1 PS4 [93] 0 PS5 [94] M0SI0 PS6 [95] 0 PS7 [96] 0 PM0 [105] RXCN0 PM1 [104] TXCN0 PM2 [103] RXCN0 0 PM3 [102] TXCN0 0 PM4 [101] RXCN0 RXCN4 M0SI0 PM5 [100] TXCN0 TXCN4 0 PM6 [88] RXCN4 PM7 [87] TXCN4 Kontroll av pagat minne Wide Bus DT15 DT14 DT13 DT12 DT11 DT10 DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 IIC SD SCL KWJ0 KWJ1 KWJ6 KWJ7 DDRJ PTJ PJ0 [22] PJ1 [21] PJ6 [99] PJ7 [98] RXCN0 RXCN4 SD TXCN0 TXCN4 SCL Narrow Bus DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Internal Logic 2.5V I/O Driver 5V VDDx [107] V1 [14] Vx [106] PWM PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 DDRP PTP PP0 [4] PWM0 1 PP1 [3] PWM1 M0SI1 PP2 [2] PWM2 1 PP3 [1] PWM3 1 PP4 [112] PWM4 2 PP5 [111] PWM5 M0SI2 PP6 [110] PWM6 2 PP7 [109] PWM7 2 V2 [66] PLL 2.5V VPLL [45] /D Converter 5V & Voltage Regulator Reference VDD [83] V [86] SPI1 SPI2 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 DDRH PTH PH0 [52] 1 PH1 [51] M0SI1 PH2 [50] 1 PH3 [49] 1 PH4 [35] 2 PH5 [34] M0SI2 PH6 [33] 2 PH7 [32] 2 Voltage Regulator 5V & I/O VR [40] 12

Pagat minne Två typer av pagat minne Internt pagat minne 14 olika minnesareor om 16K kan placeras i adressarean 0x8000 0xBFFF ktuell area väljes via skrivning till PPGE registret på adress 0x30 med något av värdena 0x30 0x3D Internt pagat minne #define PPGE 0x0030 #define PPGE 0x0030 movb #0x32,PPGE 13

Externt pagat minne 48 olika externa minnesareor om 16K kan placeras i adressarean 0x8000 0xBFFF ktuell area väljes via skrivning till PPGE registret på adress 0x30 med något av värdena 0x00 0x2F De externa minnena måste ha fysiska adresser och adresseras via 13 0 i den externa adressbussen (port och PortB) samt via XDDR14 XDDR19 i PortK XDDR14 XDDR19 används då som högre adressledningar för ett chip eller för att aktivera olika chip 14