Institutionen för systemteknik

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1 Institutionen för systemteknik Department of Electrical Engineering Examensarbete Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping av Balamurali Radhakrishnan Naveen Wali LiTH-ISY-EX--13/4684--SE Linköping 2013 Department of Electrical Engineering Linköpings universitet SE Linköping, Sweden Linköpings tekniska högskola Linköpings universitet Linköping

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3 Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping av Balamurali Radhakrishnan Naveen Wali LiTH-ISY-EX--13/4684--SE Handledare: Examinator: Muhammad Touqir Pasha ISY, Linköpings Universitet Dr. J Jacob Wikner ISY, Linköpings Universitet Linköping, 14 June, 2013

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5 Avdelning, Institution Division, Department Division of Communication Systems Department of Electrical Engineering Linköpings universitet SE Linköping, Sweden Datum Date Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport ISBN ISRN LiTH-ISY-EX--13/4684--SE Serietitel och serienummer Title of series, numbering ISSN URL för elektronisk version Titel Title Svensk titel Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band Författare Author Balamurali RadhakrishnanNaveen Wali Sammanfattning Abstract An all-digital phase locked loop for WiGig systems was implemented. The developed all-digital phase locked loop has a targeted frequency range of 2.1-GHz to 2.5-GHz. The all-digital phase locked loop replaces the traditional charge pump based analog phase locked loop. The digital nature of the all-digital phase locked loop system makes it superior to the analog counterpart.there are four main parts which constitutes the all-digital phase locked loop. The time-to-digital converter is one of the important block in all-digital phase locked loop. Several time-to-digital converter architectures were studied and simulated. The Vernier delay based architecture and inverter delay based architecture was designed and evaluated. There architectures provided certain short comings while the pseudo-differential time-to-digital converter architecture was chosen, because of it s less occupation of area. Since there exists a relationship between the size of the delay cells and it s time resolution, the pseudo-differential time-to-digital converter severed it s purpose. The whole time-to-digital converter system was tested on a 1 V power supply, reference frequency 54-MHz which is also the reference clock F ref, and a feedback frequency F ckv 2.1-GHz. The power consumption was found to be around 2.78 mw without dynamic clock gating. When the clock gating or bypassing is done, the power consumption is expected to be reduced considerably. The measured time-to-digital converter resolution is around 7 ps to 9 ps with a load variation of 15 ff. The inherent delay was also found to be 5 ps. The total output noise power was found to be -128 dbm. Nyckelord Keywords ADPLL, TDC, DPLL, PLL

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7 Abstract An all-digital phase locked loop for WiGig systems was implemented. The developed all-digital phase locked loop has a targeted frequency range of 2.1-GHz to 2.5-GHz. The all-digital phase locked loop replaces the traditional charge pump based analog phase locked loop. The digital nature of the all-digital phase locked loop system makes it superior to the analog counterpart.there are four main parts which constitutes the all-digital phase locked loop. The time-to-digital converter is one of the important block in all-digital phase locked loop. Several time-to-digital converter architectures were studied and simulated. The Vernier delay based architecture and inverter delay based architecture was designed and evaluated. There architectures provided certain short comings while the pseudo-differential time-to-digital converter architecture was chosen, because of it s less occupation of area. Since there exists a relationship between the size of the delay cells and it s time resolution, the pseudo-differential time-to-digital converter severed it s purpose. The whole time-to-digital converter system was tested on a 1 V power supply, reference frequency 54-MHz which is also the reference clock F ref, and a feedback frequency F ckv 2.1-GHz. The power consumption was found to be around 2.78 mw without dynamic clock gating. When the clock gating or bypassing is done, the power consumption is expected to be reduced considerably. The measured time-to-digital converter resolution is around 7 ps to 9 ps with a load variation of 15 ff. The inherent delay was also found to be 5 ps. The total output noise power was found to be -128 dbm. v

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9 Acknowledgments We would like to thank a lot of people: Dr. J Jacob Wikner for his precious help and support throughout the span of master thesis at different stages technically as a mentor and examiner. Muhammad Touqir Pasha for supervising throughout the project providing study materials and basic knowledge on work. Also we would like to thank Niklas U Andersson for his help. Family and friends for their all kinds of help and support. vii

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11 Contents 1 Introduction Motivation- Moving to Time Domain Project Specification Contributions of the Thesis Organization of Thesis Phase locked loops Introduction Applications Clock Generation Clock Recovery De-skewing Jitter reduction Analog Phase Locked Loop Phase/Frequency Detector Charge Pump Phase/Frequency Detector with Charge Pump Loop Filter Voltage Controlled Oscillator Frequency Divider Linear Model of Analog PLL in S-Domain Digital Phase Locked Loop Time-to-Digital Converter Digital Loop Filter Digitally Controlled Oscillator Comparison of Analog and Digital Phase Locked Loop Results Analog PLL - High-level Design Performance Parametric of DPLL Conclusion Time-to-digital converters Introduction TDC Working Principle ix

12 x Contents 3.3 TDC Resolution Buffer Delay Line Based TDC Vernier Delay Line Based TDC Inverter Delay Line Based TDC Conclusion Pseudo-differential TDC building blocks Introduction Time Quantizer An Inverter as an Time Quantizer Inverter mismatch Inverter Jitter Power consumption Sense amplifier flip flop (SAFF) as comparators Switching speed Metastability DC Offset voltage occurrence Offset cancellation Architectures SAFF Jitter Variance Power Consumption Effect of noise on TDC Quantization Error Power Jitter effect on TDC Power consumption of TDC system Conclusion Implementation, Simulation and Performance Inverter Chain Schematic Results for Inverter delay chain Inverter mismatch Inverter Jitter Sense Amplifier Flip Flop Sense Amplifier Flip Flop Implementation Sampling Window Simulation of DC Offset Voltage Pseudo-Thermometer Code Edge Decoder Implementation and Performance Power Consumption of TDC Conclusion Conclusion Conclusion Future Work

13 Contents xi A Appendix 63 A.1 Verilog A source code of PFD with CP [29] A.2 Verilog A source code of VCO [29] A.3 Verilog A source code of divider [29] A.4 Verilog A source code of PFD-CP jitter [29] A.5 Verilog A source code of VCO-FDN jitter [29] A.6 Verilog A source code of Thermometer to Binary Encoder [29] Bibliography 72

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15 List of Figures 1.1 Digital signal processing system in a mixed signal shell for analog interfacing Block diagram of analog-to-digital converter [7] Basic block diagram of analog phase locked loop Frequency Synthesis based analog phase locked loop Characteristics of Phase/Frequency Detector [19] Output of XOR gate as Phase/Frequency Detector [19] Implementation of XOR as phase/frequency detector [19] Structure of charge pump with current sources [19] Structure of phase/frequency detector with charge pump [19] Output response of phase/frequency detector with charge pump [19] First order RC low pass filter Block diagram of voltage controlled oscillator Characteristics of voltage controlled oscillator [19] Block diagram of frequency divider Linear Model of 1st type PLL in S-domain Block diagram of TDC based ADPLL [8] Block diagram of accumulator based ADPLL [8] Block diagram time-to-digital converter with normalization [22] Fractional positive phase error estimation [22] Fractional negative phase error estimation [22] General block diagram of phase detection Block Diagram of FIR and IIR filter [17] Capacitance change of an LC oscillator [22] MOS varactors vs. control voltage (deep-sub micron) [22] Test Bench of high-level Analog PLL Output Frequency of VCO in analog PLL Tuning Range of VCO in analog PLL Simulation window of CppSim Output of closed loop frequency response Output phase noise of synthesizer Closed loop pole and zero locations in S-plane Closed loop step response Working principle of TDC [28] Quantized transfer characteristics of TDC [22] Buffer delay line based TDC [28] Dual chain vernier delay line based TDC [13] Inverter based pseudo-differential TDC [28] Circuit-level of current controlled sense amplifier Modified sense amplifier flip-flop Metastability condition in current controlled sense amplifier

16 2 Contents 5.1 Schematics of cascaded inverter stages to increase drive strength Monte Carlo analysis of single inverter delay cell mismatch Edge-to-Edge jitter variance in inverter chain, J EE Cycle-to-Cycle jitter variance in inverter chain, J CC Total output noise of inverter delay cells Circuit implementation of SAFF stage1 as pulse generator Circuit implementation of SAFF Stage2 as slave latch Test bench of sampling window technique SAFF outputs with a load of 200 ff Monte Carlo histogram of offset voltage mismatch Timing diagram of TDC core signals [20] Test bench of pseudo-thermometer decoder Synthesized circuit of 6-bit pseudo-thermometer decoder Results of 6-bit pseudo-thermometer decoder Simulated result of TDC transfer function Power consumption of TDC at various frequencies List of Tables 1.1 Project specification Working of PFD with CP [19]

17 Contents 3 Acronyms PLL Phase Locked Loop VCO Voltage Controlled Oscillator PFD Phase Frequency Detector RF Radio Frequency LPF Low Pass Filter CP Charge Pump DCO Digitally Controlled Oscillator DPLL Digital Phase Locked Loop ADPLL All-Digital Phase Locked Loop TDC Time to Digital Converter DLF Digital Loop Filter FCW Frequency Command Word CMOS Complementary Metal Oxide Semiconductor MOS Metal Oxide Semiconductor VLSI Very Large Scale Integrated Circuits db Decibel CRC Clock Recovery Cycle FIR Finite Impulse Response IIR Infinite Impulse Response OTW Oscillator Tunning Word PVT Process Voltage Temperature LSB Least Significant Bit ADC Analog to Digital Converter SAFF Sense Amplifier Flip Flop DC Direct Current

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19 Chapter 1 Introduction 1.1 Motivation- Moving to Time Domain Time-to-digital converters (TDC) certainly these days have been linked only to all-digital phase locked loop (ADPLL) where, a TDC acts as phase detector, but interestingly time-to-digital converters have been used for more than 20 years in the field of particle and high-energy physics, where precise time-interval measurements are required [10]. Also, there are other applications which require time calibrations such as digital oscilloscopes and logic analyzers. All these above mentioned applications require very precise and accurate time measurements which makes TDC an essential component. Keeping these things in mind currently the micro-electronics community have rediscovered time-to-digital converters. While the all-digital phase locked loop is the most famous application of TDC due to which other applications follow rapidly. TDC based analog-to-digital converter shows that TDCs are not only used as phase detectors but useful in other important areas as well. That being said the motivating question now why, TDCs have become popular in the mainstream of microelectronics. The reason for this are the various advantages of the digital solutions compared to the analog circuits. The design of digital circuits are highly automated and as a result of which we obtain high productivity and design efficiency. However, the main advantage of digital signal processing is the inherent robustness of the digital signals against any disturbances such as noise and matching. On the other side signal integrity and variability are critical issues in digital circuits. But even then comparing to analog realizations digital solution are still robust [10]. These signal integrity and variability issues are tackled efficiently these days by many techniques which makes the digital solution an ideal medium. All these advantages of most digital signal processing systems are realized according to the Figure1.1 [7] [10]. It describes how the mixed signal shell provides the interfacing between analog and the digital core. While the data conversion is done by the mixed signal interface, the actual signal processing task is done in the digital domain. This generic system has been successful for many years and produced results, but what makes the time-to-digital converters a necessity is the reason in the technology scaling in 5

20 6 Introduction Figure 1.1. Digital signal processing system in a mixed signal shell for analog interfacing. the ultra deep sub-micron process. With each technology generation the intrinsic gain of the transistor namely the gm g d s decreases. This results in parasitic short channel effects and the fundamental MOS theory is being challenged. As shown in the figure 1.2, an ADC is the component which converts the analog value to a digital value. This is done by sampling process, which is the discretization of the time domain done using a sample and hold circuit. After which the discrete set of values are quantized, which is normally done by comparators. This quantized data represents the digital equivalent of the analog signal [7]. Figure 1.2. Block diagram of analog-to-digital converter [7]. In this thesis, we are interested in the applications of time-to-digital converters in all-digital phase locked loop. Also, the discussion of digital PLL over analog PLL will also be discussed because of the TDCs role in the latter. 1.2 Project Specification In this project, design and simulations of TDC of an All-digital PLL are carried out in 65nm process node can be seen in Table 1.1. The input reference frequency is given to be 54-MHz. Various TDC architectures are discussed in the work. The TDC is tested for different process corners.

21 1.3 Contributions of the Thesis 7 Table 1.1. Project specification. Item Min Typ Max Unit Supply voltage V Reference frequency MHz Output frequency 2-3 GHz Long-term jitter - < 3 - ps Temperature range deg 1 Time resolution 7-10 ps 1.3 Contributions of the Thesis The main objectives carried out in this work are as follows. Selection of appropriate architecture for TDC in all-digital PLL.. The selection of the appropriate architecture is based on the specifications like reference frequency, output frequency, time resolution, area and power consumption. Considering all the above requirements and choosing a less complex but effective architecture on area and power consumption is the pseudo-differential TDC architecture [7]. Modeling of chosen TDC architecture in Verilog-A using Cadence. Following the top down design approach, the chosen architecture has to be tested using a high level modeling such as Verilog-A. Before testing the chosen architecture some of the well known architectures like the vernier delay line and buffer delay line architectures were modeled to so see whether they can be used in the ADPLL system. The constraint with the above said architectures is that it consumes huge delay chain thereby taking up a huge area and power consumption. Unless if there is an efficient way to dynamically switch off some of the components in the delay chain this proves inefficient, when incorporated in a big system. There are other architectures like time windowed and time interleaved TDCs which can be used as stand alone system rather than in ADPLL because of it s complex design. Design and implementation of schematic level circuits of TDC and sub-blocks for a better performance to fulfill the required specifications. The high level model of the pseudo-differential TDC was modeled and tested and moved to schematic modeling. One of the most important block is the sense amplifier flip flop (SAFF) which ensures the symmetry at the outputs thereby avoiding metastable states. To design a TDC for an all-digital PLL system to achieve a resolution of 7 ps to 10 ps.

22 8 Introduction A time resolution of 7 ps to 10 ps was achieved to cover one full DCO cycle so that, the difference signal is time quantized to achieve the required number of bits. 1.4 Organization of Thesis The thesis will be organized as follows. Chapter 1 gives the motivation behind the thesis work, main contributions and organization of the work. Chapter 2 shows the over-all idea and working of analog PLL and digital PLL with their sub-blocks. It also explains how digital PLLs are advantageous over analog PLL. Simulations results of integrated analog PLL and performance para-metrics of DPLL are shown. Chapter 3 discusses the working principle and time resolution of TDC. Various TDC architectures are explained in detail based on their working, advantages and disadvantages compared to others, mainly discussed with respect to time resolution. Chapter 4 shows the detailed explanation of chosen pseudo-differential TDC architecture and its sub-blocks like sense amplifier based flip flop and inverter. It also gives the idea of how the performance para-metrics like metastability, DC offset, jitter, power consumption, and switching speed. Chapter 5 evaluates the schematic design and implementation of TDC sub-blocks like inverter chain, SAFF, pseudo-thermometer edge decoder. Simulation results are shown on how the performance varies depending on these parameters. Chapter 6 concludes with the future work.

23 Chapter 2 Phase locked loops 2.1 Introduction In 1930 s the major issue of synchronizing different signals in electronics and communication field was resolved by the phase locked loop (PLL). Phase locked loop are used in many applications like frequency synthesis, clock recovery, clock generation, de-skewing, jitter reduction etc [19]. Is a feedback control system which generates the output signal whose phase is compared with the phase of the input signal. The circuit compares the phase of the input signal with the phase of the signal obtained by the oscillator and adjusts it with respect to input signal in order to keep the phase matched [4]. The basic PLL circuit consists of phase detector (PD), loop filter (LP), and voltage controlled oscillator (VCO) as shown in figure 2.1. Figure 2.1. Basic block diagram of analog phase locked loop. In basic PLL, the input reference signal (Fref) and the VCO output signal (Fout) are compared to give error signal. The output of the phase detector is low pass filtered by the loop filter (LP) and give the control signal, which is used to drive the voltage controlled oscillator (VCO). The comparison is made frequently till the system gets locked i.e., when both reference signal and output signal are almost equal or zero. 9

24 10 Phase locked loops 2.2 Applications Phase locked loop s are widely used for frequency synchronization and signal conditioning, clock recovery, clock generation, clock distribution, de-skewing, jitter and noise reduction and so on [4] Clock Generation Different electronic systems including processors operate at various frequencies. A PLL is used to generate clocks for these systems. These phase locked loop multiply a lower-frequency reference clock up to the operating frequency of the processor. The multiplication factor is quite high [4] Clock Recovery High serial data streams are sent to the receivers without any clock, from the magnetic head of a disk drive to the receiver. At the receiving end, a clock has been generated from the data which is almost equivalent to the frequency of the reference signal and eventually the phase locked loop (PLL) aligns the transitions in data stream which is said to be clock recovery. To work properly the stream of data must have a transition frequency which is sufficient enough to rectify the drift in the phase locked loop oscillator [4] De-skewing The difference variation in arrival time of a clock signal is known as clock skew. Process variation like voltage and temperature results in finite delay between the clock edge and received data. The clock signal should be received and amplified before the data is driven by the flip-flops, specially where the signal and data are to be sent in parallel. The PLL at the receiver end must be set, such that the clock at each flip-flop is phase matched to the received clock to eliminate the delay [4] Jitter reduction One of the major concerns of the PLL. Clock jitter refers to the temporal variation of the clock period at a given point on the chip i.e. the clock signal can be reduced or expanded on the cycle basis. Clock recovery circuit (CRC) produces the clock from the data itself. Phase locking with a narrow loop band width, input jitter effect of the recovered clock will be reduces by the clock recovery circuit [19]. 2.3 Analog Phase Locked Loop The block diagram of frequency synthesis based PLL is as shown in figure 2.2. This PLL consists of phase/frequency detector (PFD), charge pump (CP), analog loop filter (LPF), voltage controlled oscillator (VCO) and frequency divider with a division ratio of N.

25 2.3 Analog Phase Locked Loop 11 Figure 2.2. Frequency Synthesis based analog phase locked loop. In this system, the phase/frequency detector (PFD) compares the phase of the input reference signal (Fref) and the phase of the output signal (Fout) to give an error signal. This error signal is applied to the charge pump which in turn charges or discharges the loop filter (LPF). The loop filter gives control signal by removing unwanted high-frequency signals. This control voltage is used to drive voltage controlled oscillator (VCO). The frequency of the VCO is then divided by frequency divider (FD) with a ratio of N. The output of the divider is again compared with the input reference signal. The control signal of the VCO changes as the error signal changes. The system is said to be in locked state, when the error signal is too small or zero. F ref = F out N (2.1) Equation (2.1) determines the condition for the locked state Phase/Frequency Detector The phase/frequency detector is the main block of the PLL. It plays a vital role because of its non-linearity issues. The PFD is a circuit which compares two different input signals producing a difference signal. This difference signal is proportional to the phase difference of the two signal applied. These two signals are input reference signal and signal from voltage controlled oscillator which is divided by the frequency divider of ratio N. The average output V out of the PFD is linearly proportional to the phase difference φ. The characteristics of phase/frequency detector is shown in figure 2.3. The gain of the phase detector is K pd expressed in rad/sec. The simple basic phase detector is designed using exclusive OR (XOR) gate. The width of the output pulse is proportional to the phase difference between the input pulses. The XOR circuit produces both rising and falling edges [19]. The output of the XOR gate as phase/frequency detector is shown in figure 2.4. The simple implementation of phase frequency detector (PFD) is done using edge-triggered, resettable D-flip flops with its D input always connected to logic 1. The Inputs A and B are used as clocks for the flip-flops and Q A and Q B are as shown in figure 2.5. This PFD has four states as follows;

26 12 Phase locked loops Figure 2.3. Characteristics of Phase/Frequency Detector [19]. Figure 2.4. Output of XOR gate as Phase/Frequency Detector [19]. Q A = 0 and Q B = 0 Q A = 1 and Q B = 0 Q A = 0 and Q B = 1 Q A = 1 and Q B = 1 When both Q A and Q B are logic 1 then, the circuit is reset. Thus, Q A and Q B are simultaneously high for a short duration of time but the difference between their average values represents the input phase difference correctly Charge Pump A charge pump is a circuit mainly used for voltage to current conversion. The circuit mainly consists of two current switches S 1 (source current) and S 2 (sink current) connected in series as shown in figure 2.6. The switches S 1 and S 2 are used to pump-in or pump-out the current into the loop filter respectively. If the Input reference signal leads output signal, the up signal gets activated and which in turn pumps-in current into the filter. If the output signal leads the input reference signal, the down signal gets activated which in turn pumps-out the current from

27 2.3 Analog Phase Locked Loop 13 Figure 2.5. Implementation of XOR as phase/frequency detector [19]. Figure 2.6. Structure of charge pump with current sources [19]. the filter.

28 14 Phase locked loops The output of PFD is given to the charge pump to convert the pulses into current which is then used by the loop filter. The PFD outputs up and down signals to the charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter [11] Phase/Frequency Detector with Charge Pump The phase frequency detector is connected to a charge pump which consists of two current sources S 1 and S 2 followed by driving capacitor C P as shown in figure 2.7 and 2.8. The working of PFD with a charge pump is shown in table Where I 1 and I 2 are source and sink current respectively. Figure 2.7. Structure of phase/frequency detector with charge pump [19]. Table 2.1. Working of PFD with CP [19]. PFD Outputs (Q A and Q B ) Switches (S 1 and S 2 ) Charge pump output (V out ) Q A =0, Q B =0 S 1 =OFF, S 2 =OFF V out remains constant. Q A =1, Q B =0 S 1 =ON, S 2 =OFF I 1 charges cap. C P. Q A =0, Q B =1 S 1 =OFF, S 2 =ON I 2 discharges cap. C P Loop Filter The loop filter basically used is low-pass filter which passes the low-frequency signals attenuating high frequency signals. The main principle is the cut-off frequency of the filter is approximately equal to the maximum frequency of the VCO, which

29 2.3 Analog Phase Locked Loop 15 Figure 2.8. Output response of phase/frequency detector with charge pump [19]. means the filter rejects the frequencies above maximum frequency of the VCO [18]. The filter used here is a first-order RC filter as shown in figure 2.9, which receives the current from the charge pump and gives the control voltage to VCO for oscillation. Figure 2.9. First order RC low pass filter Voltage Controlled Oscillator A voltage controlled oscillator is an electronic oscillator designed to control the oscillation frequency by voltage input [18]. This block is considered as the heart of the PLL. The oscillation frequency changes depending on the input voltage applied to it. The output of VCO is given to PFD using a closed loop feedback system. The block diagram of the VCO is shown in figure An ideal voltage controlled oscillator is a circuit whose output frequency is linear function of its control voltage [19]. ω Out = ω 0 + (K V CO V Cntrl ) (2.2)

30 16 Phase locked loops Figure Block diagram of voltage controlled oscillator. K V CO = ω 1 ω 2 V 1 (2.3) φ O = V 1 K P d = ω 1 ω 2 K V co K P d (2.4) Figure Characteristics of voltage controlled oscillator [19]. The characteristics of voltage control oscillator is plotted between output frequency ω Out versus input voltage V Cntrl as shown in figure The frequency range, (ω 1 - ω 2 ), is called tunning range. The oscillation frequency increases as the voltage increases [19] Frequency Divider A frequency divider is placed after VCO in a feedback loop which divides the output frequency ω Out by a factor of N. The divider output is connected to the PFD. The output of frequency divider is F divider = F Out N is equal or nearly equal to the input reference signal F ref. The block diagram of frequency divider is shown in figure 2.12.

31 2.3 Analog Phase Locked Loop 17 Figure Block diagram of frequency divider Linear Model of Analog PLL in S-Domain A simple linear model of 1st type PLL is modeled. The PFD output contains both dc component and the high frequency components, whose dc component is approximately equal to, K P D (φ out - φ input ) and the high frequency components are attenuated by LPF. The PFD is modeled using a substractor whose output is 1 amplified by gain K pd. The transfer function of LPF and VCO is given by 1+SRC where, ω = 1 RC and K V CO S respectively. A linear model of 2nd order PLL is as shown in figure Figure Linear Model of 1st type PLL in S-domain. The open loop transfer function is given by, H(S) open = φ out φ input (S) = (1 + S ) K P DK V CO ω LP F S (2.5) with one pole at S = - ω LP F and another at S = 0. Since the loop gain contains one pole at the origin, hence the system is called 1st type PLL. The closed loop transfer function is given by, H(S) closed = 1 + H(S) open (2.6)

32 18 Phase locked loops H(S) closed = 1 + (1 + S ) K P DK V CO ω LP F S K P D K V CO ω LP F = (S 2 + Sω LP F + K P D K V CO ω LP F ) H(S) = ω 2 n (S 2 + 2ζω n S + ω 2 n) (2.7) (2.8) ω n = K P D K V CO ω LP F (2.9) ζ = 1 ωlp F 2 K P D K V CO (2.10) comparing equation 2.7 and 2.8, we get, natural frequency ω n and damping ratio ζ. 2.4 Digital Phase Locked Loop Due to the rapid growth of integrated circuits with increasing performance, speed, reliability and decreasing size, cost has shifted its strong interest from analog to digital domains. Previously, the phase locked loop where designed in both analog and digital domains. A digital version of the phase locked loop have resolved the problems with its analog counterpart. The main reason behind hopping to digital domain is due to its flexibility and versatility with different components. One of the main advantage of digital phase locked loop above analog counterparts is that they remove the need of large capacitors within the loop filter by utilizing digital circuits to achieve the desired filtering function [8]. In ADPLL, the time-to-digital converter (TDC) is replaced by phase frequency detector (PFD) and charge-pump (CP), digital loop filter (DLF) with analog filter and digitally controlled oscillator (DCO) replacing voltage controlled oscillator (VCO). ADPLL architectures can classified into TDC-based and accumulator based, as shown in figure 2.14 and 2.15 respectively [8]. The main difference between these two architectures is how the phase error is between the reference and feedback signals is generated. In TDC-based ADPLL, the TDC output is proportional to the phase error. In this case, the phase error is achieved by measuring the delay between the positive (or negative) edges of the reference oscillator and the divider. In accumulator-based ADPLL, the phase error is determined by means of difference between the reference and feedback phase signals. In this case, the phase accumulators generate the phase signals directly Time-to-Digital Converter Time-to-digital converter (TDC) is most critical block from the digital-phase locked loop (DPLL). The main principle of TDC is to measure the edge time

33 2.4 Digital Phase Locked Loop 19 Figure Block diagram of TDC based ADPLL [8]. Figure Block diagram of accumulator based ADPLL [8]. difference between the reference frequency and the high-speed DCO clock. The other condition is to lock the two signals and produce zero phase, if both DCO clock signal and reference signal are of same phase. The TDCs fractional delay difference ε between the reference clock (Fref) and the next significant edge of the DCO clock (Fckv) is measured using time-todigital converter (TDC) with a time quantization resolution t res of an inverter delay t inv and the digital word is time difference. The integer output of time-todigital converter (TDC) cannot be used in system during its process because the time resolution is a varying parameter. Thus, it is normalized by the DCO clock period. Only the fractional error is used by the phase detector [22]. The working operation of the TDC is shown in figure 2.16, 2.17 and The smallest time interval that has to be readily resolved in digital fractional phase detector is TDC inverter delay t inv. The number of buffers or inverters forms the backbone of the simplest implementation of time-to-digital converter.

34 20 Phase locked loops Figure Block diagram time-to-digital converter with normalization [22]. Figure Fractional positive phase error estimation [22]. Figure Fractional negative phase error estimation [22]. In digital deep-sub micron CMOS, the inverter could be considered as basic precision time-delay cell with fully digital-level regenerative properties [22]. It is possible to achieve better resolution than inverter delay for the TDC function. The improvement of resolution of can be achieved by using a vernier delay line with two non-identical buffer chains. The slower chain is stabilized by negative

35 2.4 Digital Phase Locked Loop 21 feedback through a delay line. The time difference between the buffer of the upper chain and lower chain gives the resolution. The disadvantage of this method is because of higher power consumption and extra analog circuit. Reference Edge Estimation to reduce Power Consumption The prediction of reference signal Fref of TDC reduces the power consumption. This actually works due to periodic gating of the digitally controlled oscillator (DCO) clock in TDC by predicting the next reference edge lies because all the information is available from the edges of the Fref clock. After certain time of execution, the information which is far could be gathered in both clock phases which in turn reduces the power consumption and noise [22]. Phase Error Detector Frequency synthesizer is a circuit which generates one or more frequencies f V from a reference frequency f R.To achieve required DCO frequency f V, the FCW (Frequency Command Word) must be pre-defined and then used as an input to the ADPLL system by the equation [7], F CW = f V f R (2.11) The FCW determines how many number of high-speed clocks are stored in one reference frequency f R. In a system, the phase error is obtained by comparing reference phase and variable phase. The phase error of the detector is mathematically written as, ˆ φ E [k] = R R [k] R V [k] + ε[k] (2.12) The block diagram of phase detector is shown in figure This phase detector consists of three phase sources like reference phase R R [k], variable phase R V [k] and fractional error correction ε[k]. The variable phase R V [k] works by DCO clock (CKV) and is later re-clocked by CKR clock. Later in the end all the three phase sources are synchronized with CKR clock [7]. Reference Phase Block This reference accumulator block is implemented by R R. It can be obtained by accumulating frequency command word (FCW) as in equation 3.3. k R R [k] = F CW (2.13) l=1

36 22 Phase locked loops Figure General block diagram of phase detection. Variable Phase Block Variable phase accumulator R V [k] is implemented with first stage with an accumulator and flip-flop at the second stage. The main purpose of variable phase accumulator is to count the increments of the DCO clock. Fractional Error Correction R V [i] = i 1 (2.14) Fractional error correction (ε) is measured by means of time-to-digital converter (TDC) between reference signal (Fref) and DCO clock (Fckv). The TDC has a chain, if inverters with propagation delay as the time reference. Resolution of one of the inverter delay t inv is the time quantization resolution of the TDC, t res. In operation, the inverter in within the chain will have variance in propagation delay. Therefore, the digital representation of the TDC output could not be used directly as fractional error correction (ε). The digital output code of TDC must be normalized by the oscillator clock period (T v ). l=1 ε = 1 ( t r T v ) (2.15) From figure 2.17 and 2.18, t r is quantized time delay between the rising edge of the DCO clock and the FREF sampling edge, whereas t f is the time delay between the falling edge of the DCO clock and the FREF sampling edge with a

37 2.4 Digital Phase Locked Loop 23 resolution of t inv. In this system, t r and t f are determined by the transition from 1 to 0 and 0 to 1 respectively. { tr t T V = f t r t f t f t r otherwise Information regarding rise time t r and fall time t f of TDC can be used to calculate the half period of DCO clock using the condition above mentioned Digital Loop Filter In an ADPLL, a digital loop filter is used after time-to-digital converter, which is used to remove the unwanted frequency components. The main principle of the filter is for signal separation and restoration. The signal separation is to remove interferer (unwanted signal) from the wanted signal and restoration signal is to remove the distortions from the received signal to get the actual required signal. The low-pass filter is a system whose magnitude attenuates with the increase in frequency. The filter allows low-frequency signals attenuating the high-frequency above the cut-off frequency. Cut-off frequency is the frequency at which the filter s frequency response drops by 3 db below the pass band. The amount of attenuation for each frequency is not constant. It varies from filter to filter. A digital filter performs mathematical computations on the discrete- time signal to modify the properties of that signal whereas, analog filter uses continuous time signals. The continuous time signal can also be processed by digital filters by first digitizing and converting to a sequence of numbers and then passed through the digital filter. The output of the digital filter is converted back to analog signal. The output from the digital filter is converted back to an analog signal. The design and features of a digital filter depend upon the application for which the filter is employed. Characterization Of Digital Filters To characterize the digital filter, a transfer function is used. Transfer function determines the relation between the input and output of the linear time invariant (LTI) system. Designing a filter requires the knowledge about its frequency response, impulse response, stability and so on. The transfer function of the LTI digital filter expressed in Z-domain is shown below [1], H(Z) = Y (Z) X(Z) = Y 0 + Y 1 Z 1 + Y 2 Z Y N Z N 1 + X 1 Z 1 + X 2 Z X M Z M (2.16) From above equation, the order of filter is greater than N or M. The above transfer function of the filter with numerator (output) and denominator (input) represents infinite impulse response (IIR) filter, whereas if the denominator is made to unity i.e. no feedback, which represents finite impulse response (FIR) filter.

38 24 Phase locked loops Types of Digital Filters Filters are usually classified in several groups like impulse response, frequency response and step response, depending on which criteria are used for classification. The two major classification are impulse response digital filters (FIR filters) and infinite impulse response digital filters (IIR filters) [17]. Both the filters have some pros and cons, which are carefully considered when designing a filter. Basically, it is important to consider all the fundamental characteristics of a signal to be filtered, which will be very important factor in deciding which filter to use. In many cases, the only important characteristics that matters is linear phase characteristic of the filter or not. The basic characteristics of FIR filters are, Linear phase characteristics High filter order (more complex circuits) and Stability. The basic characteristics of IIR filters are, Non-linear phase characteristics Low filter order (less complex circuits) and Resulting digital filter has the potential to become stable. Figure Block Diagram of FIR and IIR filter [17] Digitally Controlled Oscillator A digitally controlled oscillator (DCO) is implemented using only digital components. It is a key component used in ADPLL. From theoretical information, this is a efficient mechanism to represent a signal containing both phase and frequency. The time-domain resolution is more superior than the voltage-domain resolution. The digitally controlled oscillator implemented consists of digital outputs and inputs operating in discrete-time domain, even though the main functionality is continuous time and amplitude in nature. This important consideration is such that it stops the analog nature [22]. A digitally controlled oscillator (DCO) is mainly used to perform digital-tofrequency conversion (DFC). It outputs a periodic waveform, whose frequency f is a function of the input oscillator tunning word (OTW).

39 2.4 Digital Phase Locked Loop 25 frequency, f = F (OT W ) (2.17) F(OTW) is a non-linear function of an input, which traces the digital input to the frequency oscillation. The frequency setting function was not known precisely and differ with the process spread, voltage and temperature. An instantaneous value of the frequency lies on power or ground and substrate noise, flicker noise and thermal noise as well [22]. Digitally Controlled Oscillator Gain and Transfer Function Digitally controlled oscillator is the important part of the frequency synthesizer, which is designed with digital components. It generates the output frequency of oscillation f v, which is inherent function of digital oscillator tunning word (OTW). f v = F (OT W ) (2.18) It can be considered as a linear function in the limited operating range. The DCO gain can be represented as k DCO. f v = f o + k DCO (OT W ) (2.19) From above equation, f v is frequency deviation of center frequency and f o is adjustable center frequency. k DCO is a frequency deviation of f v in hertz from a certain oscillating frequency f v in response to 1 LSB input change. Due to this, k DCO is same as f frequency resolution. In the linear operating range, the gain of the oscillator is expressed as: K DCO (f v ) = f v (OT W ) (2.20) K DCO (f v, (OT W )) = f v (OT W ) (2.21) So in a limited range, k DCO must be linear with respect to the input. Since the DCO gain is also a function of (OTW), k DCO can be written as in the Equation (2.21). Digitally Controlled Oscillator Tunning Word Re-timing DCO input tuning word re-timing method is an idea based on changing the tuning control input of a digitally controlled oscillator to adjust its phase and frequency in normal operation of the PLL. The normal operation of the PLL was considered as a disturbing action that produces an output with huge jitter or phase noise. This could be very well recognized in the DCO, where the frequency oscillation changes with respect to discrete intervals. Since the oscillating frequency of a LC tank was controlled by varactors which does the function of voltage to capacitance conversion. The total charge should be stored, by changing the capacitance at these time causes the electrical potential to exhibit the largest change V = Q C, as shown

40 26 Phase locked loops in figure These perturbations were translated by the oscillator circuit into timing jitter. By changing the capacitance of the varactor during the time when it gets discharged entirely would affect the voltage slightly and thus eventually contribute very little to the oscillating jitter [22]. Figure Capacitance change of an LC oscillator [22]. Design of varactors in deep-sub micron CMOS process Figure MOS varactors vs. control voltage (deep-sub micron) [22] The challenging task of the low-voltage deep-sub micron CMOS oscillator is frequency tunning, due to its highly non-linear frequency vs. voltage characteristics, thus oscillator must be carefully designed. The characterization of MOS varactors vs. control voltage for both traditional and deep-sub micron process is

41 2.5 Comparison of Analog and Digital Phase Locked Loop 27 shown in figure Thus, a large linear range gives the oscillator a wide and precise tunning of a frequency. 2.5 Comparison of Analog and Digital Phase Locked Loop The typical analog PLL implementation exhibits more problems in most of the applications. Firstly, they are very sensitive to process variations and also the problem increases once the implementation of analog PLL progress in the deepsub micron. The cost implementation is also too high due to the capacitors placed in the analog circuitry which occupies more space in the chip even-though the filter used is of first order. Thus increase in the order of PLL increases filter order resulting high capacitor size which occupies larger area in the chip. The phase locked loop in the form of digital circuitry has more advantages than the analog PLL. In digital circuits, the blocks implemented can be scaled down easily as the technology improves further. The circuits can even perform better at lower supply voltages. As a matter of linearity aspects, digital circuits are much better than the analog, whereas the linearity is very high for analog circuits. Digital PLL has shorter lock time compared to analog PLL. Digital PLL have low jitter and noise compared to analog PLL. 2.6 Results Analog PLL - High-level Design Figure 2.23 below is the test bench analog PLL designed in cadence. The subblocks like PFDCP, VCO and frequency divider are implemented and integrated in high-level design using Verilog-AMS. The division ratio of frequency divider ratio is set to 28. The input reference frequency was set to 54-MHz. The VCO tunning range was designed to be 1.5-GHz to 2-GHz. As we know fact, the loop bandwidth of the filter is one tenth of the reference frequency, thus it is set to be 10 khz and also the capacitor and resistor component values are calculated based on it using online calculator. The chosen values are given below: Capacitor, C1 = 2.26nF. Capacitor, C2 = 33.9nF. Resistor, R = Ohm. Figure 2.24 and 2.25 demonstrates the simulation results of the VCO output frequency and tuning range of analog PLL respectively. The control voltage of the VCO is obtained from the loop filter output, which is the error signal in phase and frequency between the reference frequency and the VCO frequency. Loop bandwidth of a filter determines the lock time of the PLL. It would be necessary to determine the key performance parameters like phase noise, stability, lock time and reference spurs. A trade-off arises when the stability of the PLL and their settling time appears. Faster the lock time, wider the loop bandwidth

42 28 Phase locked loops Figure Test Bench of high-level Analog PLL. Figure Output Frequency of VCO in analog PLL. but the stability is better for narrow bandwidth. Thus, initially PLL has a larger bandwidth and later it switches to lower bandwidth as is approaches lock time Performance Parametric of DPLL Various performance parametric results of Digital phase locked loop are designed using a tool called CppSim. This tool is simple and fast in designing the phase locked loop at transfer function level. This simulator uses closed loop transfer function description as a input to determine open loop parameters which are used in designing the desired PLL. Different parameters like output phase noise, poles and zeros location, closed loop frequency and step response results are plotted. The simulation window where the results of different parameters for PLL are obtained is shown in figure The following are input specification of the DPLL: Reference Frequency = 54-MHz.

43 2.6 Results 29 Figure Tuning Range of VCO in analog PLL. Output Frequency = 2.1-GHz. Loop Bandwidth = 100 khz. Filter Order = 2. DCO Phase Noise = -115 dbc/hz at 1 MHz offset [16]. TDC Phase Noise = - 95 dbc/hz. Figure Simulation window of CppSim.

44 30 Phase locked loops Closed Loop Frequency Frequency response relates to the measure of output spectrum of system in response to the stimulus, and used to characterize the system dynamics. The closed loop frequency is defined as signal frequency whose magnitude drops by 3 db from its initial value. Figure 2.27 shows the plot of closed loop frequency response obtained from input values in CppSim. Figure Output of closed loop frequency response. Output Phase Noise Figure 2.28 shows the plot of output phase noise in CppSim. Phase noise is the frequency domain representation of rapid, short-term, random variation in the phase due to to the time instabilities [27]. It causes the spectral purity degradation. Its is an important parameter in many oscillators, which affects the system performance. Phase noise can be reduced by the noise characterization through modeling and simulation of the design. The factors affecting the noise are passive components selection and resonators modeling. Poles and Zeros Location Pole-zero plot is a graphical representation of transfer function of a dynamic system in a complex plane. The poles are indicated as X and zeros as O in the plot. Polezero plot can be represented in continuous-time (CT) or discrete-time (DT system) [9]. Figure 2.29 plot is located in a S-plane.

45 2.6 Results 31 Figure Output phase noise of synthesizer. Figure Closed loop pole and zero locations in S-plane. Output Step Response Step response is also known as the time behavior of the output of the system when, its input changes from zero to one in a short period of time. Practically, one should know how the system responds due to the quick inputs is important. Such large and fast deviations for a long term steady state might effect the system

46 32 Phase locked loops itself and component [14]. To overcome such act the component must settle down to some state. This gives the information on the stability of the system. Figure 2.30 gives the idea of it. Figure Closed loop step response. 2.7 Conclusion In first section, analog PLL are explained in detail with their sub blocks, functionalities, architectures and applications in order that readers could have a good knowledge on PLL. As the discussion continues, Digital phase locked loop sub blocks like TDC, digital loop filter and DCO are briefly explained. High-level analog PLL is implemented in Cadence using Verilog-AMS. A brief justification is given, how digital PLL circuits are more advantageous than the analog PLL.

47 Chapter 3 Time-to-digital converters 3.1 Introduction In the past decades, time-to-digital converters (TDCs) are widely used for time measurement many fields like space science, instrumentation test, high-energy physics and soon. TDC is used to measure the phase error between the reference signal and the feedback signal in time domain, which directly outputs the phase error in digital format that can be processed by an on-chip programmable digital loop filter [20]. Due to this filter, the loop dynamics of the digital PLL can be easily programmed and thus to achieve low phase noise and fast settling time at the same time. It can also provide accurate loop dynamics that are less sensitive to process, voltage and temperature (PVT) variations and more immune to supply and substrate noise. In addition, the area of DPLL can be reduced by large capacitors used in loop filters. Similar to other sampling circuits, TDC generates quantization noise while digitizing the time interval between the two signals. The quantization noise is associated with the TDC resolution which limits the in-band noise of the DPLL. In other words, the finer the TDC resolution is, the better in-band noise can be achieved. 3.2 TDC Working Principle The working principle of time-to-digital converter based on digital delay line is shown in figure 3.1. The start signal is passed through a array of delay elements and are sampled at the arrival of the rising edge of the stop signal. The sampling process can be accomplished by implementation of flip-flops which freezes the state of the delay line as the stop signal occurs. The output of flip-flop will be of high value (1s) if the start signal allows the delay stages and flip-flop generates low value (0s) if the delay stages have not been passed by the start signal. As a result, the decoder measures the position of high to low transition indicating how far the start signal can be propagated in the time interval by start and stop signal. 33

48 34 Time-to-digital converters Figure 3.1. Working principle of TDC [28]. 3.3 TDC Resolution Time resolution is the important parameter in designing of TDC. Its is derived from the time difference between the reference signal and DCO clock. The transfer characteristics of TDC is shown in figure 3.2. The phase error of TDC is linear and similar to typical analog PLL. It is quantized t res time units. L max(t v) min(t inv ) (3.1) t res = t inv (3.2) The TDC quantum step is t res determines the step of the fractional error correction, which is expressed in normalized as ɛ = t res T v (3.3) Since, the reference signal period T REF remains unchanged over time, the time resolution of TDC T DC can be converted in to a phase resolution of the phase-to digital converter Φ as: Φ = 2Π T DC T REF (3.4)

49 3.4 Buffer Delay Line Based TDC 35 Figure 3.2. Quantized transfer characteristics of TDC [22]. 3.4 Buffer Delay Line Based TDC After a sufficient time of research done in past years to find a way to build a high resolution time time-to-digital converter. The simplest TDC is based on a delay line composed of buffers with delay time T DEL is shown in figure 3.3. Inverters are used in the delay line. As the start signal travels through the delay line, the output of each buffer is flipped after time T DEL. When the stop signal arrives, the outputs of all the buffers are stored in to a register and then decoded. One advantage of this TDC is that it cane designed fully digital. This architecture is elegant ans simple to implement, but it suffers from poor timing resolution due to the use of non-inverting delay elements. Figure 3.3. Buffer delay line based TDC [28].

50 36 Time-to-digital converters 3.5 Vernier Delay Line Based TDC Figure 3.4. Dual chain vernier delay line based TDC [13]. To improve the time resolution of the buffer delay line based TDC, vernier delay line based TDC is used which is capable of measuring of time interval with sub-gate resolution. The vernier delay line structure consists of a pair of tapped delay chains with a flip-flop at each corresponding pair of taps as shown in figure 3.4. The upper delay chain consists of buffers with a delay of T DEL1 while the lower delay chain has buffer with a delay of T DEL2. Assuming that F REF arrives before F CKV and T DEL1 is greater than T DEL2. As the reference signal F REF and clock signal F CKV travels through the delay lines, the time difference between these two delay chains decreases after each stage and is given by: T imeresolution, T R = T DEL1 T DEL2 (3.5) Therefore, the resolution depends on difference between the two delay stages instead of one delay element. Although the vernier delay line TDC improves resolution effectively, the power consumption and area are increased. This is because each stage costs of two buffers and a flip-flop. 3.6 Inverter Delay Line Based TDC The time resolution of inverter-based TDC is the delay of the inverter whose resolution is double compared to the buffer delay line. This architecture also known as Pseudo-differential TDC as shown in figure 3.5. In buffer-based TDC, the inconsistent transition of the rising and falling edges of the delayed signals and unbalanced metastability of the flip-flops occurs. This destroys the characteristics of TDC resolution such that inverter-based delay line TDC is more advantageous

51 3.7 Conclusion 37 Figure 3.5. Inverter based pseudo-differential TDC [28]. over the buffer-based TDC. The structure is also used to avoid any mismatch between rising and falling edge transitions. The resolution is almost equal to the CMOS inverter propagation delay, which is less than 10 ps in this CMOS process and is expected to improve as the process technology advances. 3.7 Conclusion Time-to-digital converters are considered as important block in All-digital PLL. First section gives in depth knowledge of TDC, its working principle, functionality and most important parameter time resolution associated with it. Different types of TDCs like buffer-based, vernier-based and inverter-based are explained with their pros and cons compared to each other. In second section, inverter-based TDC is chosen for thesis work because of its improved time resolution, conversion time, mismatch and soon. Detailed explanation and working of inverter-based TDC and its sub-blocks are discussed in chapter four.

52

53 Chapter 4 Pseudo-differential TDC building blocks 4.1 Introduction The architectures like pseudo-differential TDC are widely used because of their insensitivity towards NMOS and PMOS mismatches. The uniqueness of this architecture mainly depends on the limitation of the intrinsic delay of the buffer elements and the improved resolution below sub-gate delay. The proposed pseudodifferential TDC takes the advantage of deep-submicron process strengths in fast logical switching and finest logic-level regenerative timing of the inverter propagation delay. This minimizes the load on the inverter delay chain, the resolution similar to the inverter propagation delay. 4.2 Time Quantizer An Inverter as an Time Quantizer In an ADC system, resistors behaves as an reference voltage which carries out the quantization process. In any TDC system, inverters are used as the delay elements which performs the quantization process, but in the time domain. The propagation delay characteristics of an inverter is made used to perform the time quantization. The expression for inverter delay is given by the following equation 4.1 [7]. Where, C L is the total load capacitance, V DD is the supply voltage, and β n and β p are the device trans-conductance of the NMOS and PMOS respectively. V T N and V T P are the threshold voltage of NMOS and PMOS respectively. V DD V DD t pd = 1 2 (C L β n (V DD V T N ) α + C L β p (V DD V T P ) α ) (4.1) Various parameters like PVT variations, mismatch and jitter affects the propagation delay, t pd which in turn these parameters have independent and uncorre- 39

54 40 Pseudo-differential TDC building blocks lated effects on the it. Thus it becomes important to consider all the factors of inverter propagation delay t pd, which might affect the whole TDC system with some undesirable results. The mismatch and jitter combined together will introduce phase noise on the TDC system. The TDC linearity will also be affected by all these factors. When incorporated in ADPLL system, the non-linearity is caused due to the mismatches will cause fractional spurs and will affect the other connecting blocks such as the digital loop filter and so on. Also, the delay variance due to PVT will introduce gain error [7]. The following sections will cover these details Inverter mismatch The delay mismatches in an inverter are threshold voltage V T, device transconductance β, and drain current I d which produces uncertainties in propagation delay, resulting output skew from one delay cell to another. Thus linearity error appears due to uncertainties at the output [7]. The mismatch variance can derived from Equation 4-1 [6]. The derivative of the Equation 4-1 gives us the variances such as V T N, V T P, β n, β p, and C L respectively. σtpd,mis 2 = t2 pd 4 (2σ2 CL CL 2 + σ2 β n βn 2 + α 2 σv 2 T N (V DD V VT N ) α + σ2 β p βp 2 + α 2 σ 2 V T P (V DD V VT P ) α ) (4.2) From the above equation it is clear that decrease in delay variance, increases the C L, V DD and β. The standard deviation of the inverter cells vary independently due to local variations and as a result of which these variations are accumulated throughout the TDC chain of inverters. The mismatch at the N-th inverter chain can be given by the Equation 4-3 [6] [7]. σ tpd,mismatch = Nσ tpd (4.3) The total mismatch of the TDC can be found out by the sum of inverter chain mismatch variance and sense amplifier flip flop variance, as in Equation 4-4 [6] [7]. σ 2 total,mismatch = σ 2 SAF F,mismatch + σ 2 tpd,mismatch (4.4) The total mismatch variance has to be kept low or at least lower than that of the TDC resolution so that the integral error is less than one LSB [7] [10], [25]. The design of the TDC system should be based on following factors Inverter Jitter Jitter is defined as the short term variations of a digital signal s significant time instants from their ideal positions [15]. It can also be defined as the time domain manifestation.

55 4.2 Time Quantizer 41 Jitter classification There are two main types of jitter: Deterministic jitter (DJ) and random jitter (RJ). Both of these are referred to as systematic and non-systematic jitter respectively. Jitter can also be characterized in time domain by measuring the standard deviation of the jitter process using oscilloscopes. Therefore a technique for relating jitter measures from either domain is desirable, so that the designer can work in whichever domain is easiest while, still being able to accurately predict performance when measured by the end user. The timing error, in this case jitter is caused due to the noise within the inverter cells. These noise values are much lower than the noise generated by mismatch of voltage and current, but the device mismatch creates more noise [15]. The jitter variance is given by the Equation 4-5. σ 2 tpd,jitter = 4kT γtpd I(V DD VT ) (4.5) The above equation gives us an idea of how jitter will contribute to the in-band phase noise of an ADPLL system. The cycle-cycle jitter (J EE ) and the edge-edge (J CC )results are presented in the following chapters Power consumption The power consumption of an inverter is given by the Equation 4-6. P inv = C out V 2 DDf (4.6) From Equation 4-6, it is clear that the power consumption increases with operating frequency. Based on the simulation results for the power consumption in the following chapters can be seen that the power consumption increases with the TDC system for different frequencies. Therefore it is important to switch off some parts of the TDC system when not in use. However, the biggest contributor is the inverter chain since the high frequency signal is passed through the chain [7] Sense amplifier flip flop (SAFF) as comparators In an flash ADC, the conversion accuracy depends on the comparators which are used. The main attributes or design challenges of comparator are speed, offset noise, metastability and power consumption. There are various architectures of sense amplifier flip flops were designed to meet specific needs. One such is the current-controlled latch sense amplifier which were designed for low power constraints. The current-controlled latch sense amplifier is a modification of the conventional current mirror sense amplifier as shown in Figure 4.1 [7]. From the circuit it can be seen that the current flowing through the latch circuit is very small also during the switching operation on the inverters of the latch sense amplifier. During this operation no static power is dissipated. As a result of which, power consumption can be minimized also without making a trade off with the speed [7].

56 42 Pseudo-differential TDC building blocks Figure 4.1. Circuit-level of current controlled sense amplifier. There are other architectures also which focus on low power consumption and high speed switching. We also want to have a balance between the other design challenges which are mentioned in the beginning. One such architecture which strikes a balance between all those is the modified SAFF. The modified SAFF also has a low metastability window which results in no bubble at the outputs thereby making the output code near perfect. Refer to the Figure 4.2 [5] Switching speed One of the major design challenges in a comparator is the switching speed. The speed of the latches in the comparators can be determined as follows given by [26] [2]. This is expressed by the Equation 4-7. t initial = C LV th I p (4.7) t initial is delay occurred during the first phase of the operation which is proportional to load capacitance, C L and the threshold voltage of the PMOS transistor, V th. With the second cycle occurring due to the positive feedback, an initial voltage difference can be seen at the outputs. These outputs give rise to something called as the latch delay time and is described in the Equation 4-8 [7] [26] [2]. t latch = C L g m,trans ln( 2δV out V 0 ) (4.8)

57 4.2 Time Quantizer 43 Figure 4.2. Modified sense amplifier flip-flop. τ latch = C L g m,trans (4.9) The transconductance g m,trans is assumed to matched for the inverters which gives rise to the Equation 4-10 [7]. g m,trans = g m 1 r DS (4.10)

58 44 Pseudo-differential TDC building blocks Substituting Equation 4-10 in 4-9, which can be re-written as Equation 4-11 τ latch = C L g m 1 r DS (4.11) Based on the above equations, the delay is affected by the load capacitance C L, transconductance g m, input voltage δv in. t delay,total = t initial + t latch (4.12) Also, the total delay can be expressed by the Equation 4-12 [26],[2] Metastability Metastability is one of the important factors of a comparator in flash ADC. The same thing can be applied to TDC, since the system involves comparators, in our case, SAFF. Metastability is bounded by two important parameters, the setup and hold time. Whenever the setup and hold time of the flip flops are violated, the output enters into the metastability state or a quasi-stable state. It s the condition were the output stays between one and zero which is often denoted as X. At the end of sampling period X will either be one or zero. If comparator suffers from metastability then the output code may be altered. In case of ADPLL, the TDC may produce fractional spur errors which affects the other systems, thereby destabilizing the ADPLL loop [7]. A sample timing diagram for a metastable condition is shown Figure 4.3 [7]. Figure 4.3. Metastability condition in current controlled sense amplifier. Based on the comparators voltage there is an exponential increase which is given by the Equation 4-13 [24] [12] V out = V 0 exp t r (4.13)

59 4.2 Time Quantizer 45 The time taken by the metastability condition to resolve is given by the Equation 4-14, with τ is the time constant of the comparator. t 0 = τ ln( V out V 0 ) (4.14) From above equation, V 0 is the initial condition which is the overlap voltage between the clock and the data. This gives rise to Equation 4-15 and Equation 4-16 defining the metastability window given by Equation 4-17 [7] [24][12]. V 0 = aδt in (4.15) t = τ ln( V out aδt in ) (4.16) t window = V out (4.17) a The reference frequency is given by F ref and input time smaller than the sampling window t w is given by P error 1 sec = t w T V F ref = t w F ckv F ref (4.18) The above mentioned equation gives rise to mean time between failures (MTBF). When multiplied by the number of flip flop cells within the TDC system. This MTBF describes the error which, a comparator can withstand or accepted [7]. MT BF = 1 t w F ckv F ref (4.19) The simulation results in the following section shows the metastability and it s effects on TDC system DC Offset voltage occurrence Offsets are most common in operational amplifiers and in comparators. They have a built-in offset voltages and currents due to improper matching of circuit components. As a result of which even when input signals with voltage levels equal to and greater than zero, offsets are produced. Due to this they result in a variation of outputs which causes errors. Systems which requires high sensitivities are largely affected by offsets [7]. Here is an example of how it affects an detection circuit : Example 4.1 We want to detect a signal by summing magnitude over a time period. Which can be mathematically expressed as [3], t 1 t=t 0 X (4.20)

60 46 Pseudo-differential TDC building blocks From the above equation it can be inferred that, No signal 0 Signal 1 No signal +DC bias 1 Classification of offsets Offsets can be classified into two types, which are systematic and random offsets. Systematic offsets are those which are produced as a result of asymmetric design of circuit and layout. Random offsets are those which are produced as a result of variations in the fabrication process. The random offsets are mathematically explained by the following equations σ 2 V T = A2 W L + S2 V T D 2 (4.21) σ 2 β β 2 = A2 β W L + S2 βd 2 (4.22) By varying W and L,we can reduce the random offsets Offset cancellation Architectures There are two types of offset cancellation architectures [3]. They are as follows. 1. Feed-forward : In this technique a DC offset estimator is placed before the comparator such that, it receives the input signal and estimates the offset error. They are also generally faster in estimation. 2. Feed-back : In this technique the estimator receives the corrected signal making the estimation accurate. By considering both static offset voltage and the dynamic offset voltage, the overall random offset voltage can be obtained [7]. σ 2 SAF F = σ 2 M1,M3 + σ 2 M2,M4 + σ 2 M5,M6 + σ 2 C L (4.23) SAFF Jitter Variance In [7], the comparator jitter variance is derived from performing noise analysis. It is done by estimating the input referred noise of the comparator [7]. By normalizing the comparator noise ( σnoise 2 ) by the inverter, we have, σ 2 jitter = σ2 noise S 2 (4.24)

61 4.3 Effect of noise on TDC 47 By substituting S = V DD /2t d, then the SAFF jitter variance can be re-written as, σ 2 jitter = δ κt γ C C 4t 2 d V 2 DD (4.25) From the above equations,the supply voltage or the output capacitance should be varied so that the jitter variance is reduced significantly Power Consumption The power consumption of the sense amplifier flip flop(saf F ) is derived from the total delay of the current sense amplifier. In our case, the structure has two parts, the D-Latch and the SR latch which introduces a slight delay from the data to the output [7]. Refer to the figure 4.2. The overall equation can be expressed as ( ( )) 1 P SAF F = C L V thp + C L V eff ln V DD F ref (4.26) I V 0 V out thp 2β V in Based on the above equations, it s quite evident that, the power consumption is mainly due to load capacitance(c L ) and the operating frequency (F ref ). 4.3 Effect of noise on TDC Quantization Error Power All though we are dealing everything in time-domain with respect to TDC, the quantization error power of ADC can be applied to TDC as well [7]. In[1], Equation 1.27 describes the quantization error. σ 2 noise,power = t2 delay 12 (4.27) Jitter effect on TDC Jitter effect on TDC can be taken as the sum of jitter variance of inverter cells and sense amplifier flip-flop (SAF F ). Based upon the previous derivation of both the variance [7], we have σ 2 jitter,tot = δ κt γ C c 4t2 delay V 2 DD + ( ) N4κT γn t 2 delay CV DD (V DD V t ) + N.κT t2 d elay CVDD 2 (4.28)

62 48 Pseudo-differential TDC building blocks Power consumption of TDC system The total power consumption can be calculated as the same as that of the jitter variance. It s the sum of inverter chain and the sense amplifier flip-flop(saf F ) power consumption which can be mathematically described as P T DC = P inv,cells + P SAF F (4.29) The least or the minimum power consumption can be achieved, if the quantization error power is equal to the jitter variance. In such case, we can describe them mathematically by Equation 1.31 and Equation 1.32 [7] [21] [23]. σ 2 tot,jitter = σ 2 q (4.30) ( δ κt γ C c 4 V 2 DD + ) N4κT γ N CV DD (V DD V t ) + NκT CVDD 2 t 2 delay = t2 delay 12 (4.31) σ(tot,jitter 2 ) = 1 (4.32) 12 From the above equations, minimum power consumption for the entire TDC system can be found based upon the quantization error and the jitter variance. 4.4 Conclusion In first section, the inverter delay cell and its effects like mismatch, jitter variance where discussed. Secondly, sense amplifier flip flop and its working is explained in detail. The parameters like switching speed, dc offset, power consumption, and metastability state with respect to sense amplifier based flip flop are explained.

63 Chapter 5 Implementation, Simulation and Performance The simulation results and conclusion of the chosen architecture pseudo-differential time-to-digital converter and their sub-blocks like inverter delay cell, sense amplifier flip flop and pseudo thermometer to binary decoder. 5.1 Inverter Chain Schematic The inverter chain is based upon the calculation that it should cover one full DCO(Digital Control Oscillator) cycle. So that the entire DCO cycle is time quantized by the inverter propagation delay (t delay ). Inverters were used from the standard cell library of STM065nm. There are various versions of inverters are provided in the library. Based upon how far the signal has to pass through the chain, suitable inverter with a drive strength was chosen. A sample of a single inverter chain is shown in the Figure 5.1. Based upon the above said calculations, 46 inverter delay cells are used with a propagation delay of 8.56 ps. Some margin should provided such that the system can operate at worst case conditions, particularly in this design, we have provided extra 3 inverter delay cells. A approximate area size for the whole chain was found out to be 200 x 17 µm Results for Inverter delay chain Based upon how far the signal has to pass through the chain, suitable inverter with a drive strength was chosen. The simulation results of the TDC sub-block, inverter delay with parameters like delay mismatch and jitter variance are shown. 1 The area was calculated based on the dummy layout provided by the standard cell library. 49

64 50 Implementation, Simulation and Performance Figure 5.1. Schematics of cascaded inverter stages to increase drive strength Inverter mismatch Mismatch between the inverter delay element can cause undesirable result such as variation in the propagation delay (t delay ). So, in order to avoid that a Monte Carlo simulation was performed to determine the mismatch. As seen in the Figure 5.2. The simulation is performed for 500 runs which gives us a standard deviation of 2σ to 2σ, giving an yield of 88.9 %. The mismatch can be reduced by the increasing the size of the transistor but, the power consumption has to be taken into account. By knowing the standard deviation values we could substitute them in the previous equations to estimate the total mismatch variance. From the Figure 5.2, it is seen that the mismatch variance is around 500 fs, which is well within the propagation delay(t delay ) of 8.5 ps. Also it can see that for the t delay values 7 ps - 8 ps do not pass through which, gives us an idea to eliminate certain range for sizing the transistor values Inverter Jitter The jitter phenomenon classification and occurrence is already explained in Section We are interested in finding the edge-to-edge jitter (J EE ) and cycle-to-cycle jitter (J CC ). These jitter variance will then be added to the sense amplifier flip-flop (SAF F ) variance values and thus total variance will be calculated. The following figures will give an estimate of both J EE and J CC values. As depicted in Figure 5.3 and Figure 5.4. The obtained values are 74.3 fs for J EE and fs for J CC. From Figure 5.4, there are two values which is to be noted, fs is for 1 cycle and fs is for 10 5 cycles. So, this clearly shows that even after 10 5 cycles there isn t much difference in the inverter chain. This is because, the jitter values can be kept low by increasing the transistor size which, in turn will have an effect on the power consumption. It s the designers choice to have a trade-off between these factors.

65 5.3 Sense Amplifier Flip Flop 51 Figure 5.2. Monte Carlo analysis of single inverter delay cell mismatch. All of the above values correspond to the best and worst case conditions. We also want to know what is the total output noise produced by the inverter delay cells. As depicted in Figure 5.5, it produces a total output noise of dbm. 5.3 Sense Amplifier Flip Flop Sense Amplifier Flip Flop Implementation The sense amplifier flip flop is implemented into two design stages. Figure 5.6 shows the first stage which consists of the D-latch which initially senses the differential inputs. The second stage consists of the SR-latch which is depicted in the Figure 5.7. After the differential inputs are sensed by the D-Latch, the SR-Latch takes each transition into account and holds the state until it encounters the next leading clock [7]. The function is that when CLK is low, S bar and R bar will be forced to V dd due to M4 and M6. When the clock goes high, the input differential pair is on, the preset transistors are off and the inputs are compared to each other.

66 52 Implementation, Simulation and Performance Figure 5.3. Edge-to-Edge jitter variance in inverter chain, J EE. Figure 5.4. Cycle-to-Cycle jitter variance in inverter chain, J CC.

67 5.3 Sense Amplifier Flip Flop 53 Figure 5.5. Total output noise of inverter delay cells. Figure 5.6. Circuit implementation of SAFF stage1 as pulse generator. When the clock goes low, the differential pair shuts off and the output nodes are pulled up to V dd by M4 and M6. Since it s a rising edge-triggered (as the output changes at the rising edge of the clock), sampling of the differential data happens immediately after the rising edge of the clock. At this instant, the differential pair is activated and that branch which sees a higher voltage at the gate, drains more current resulting in the output node (both output nodes are pre-charged initially)

68 54 Implementation, Simulation and Performance Figure 5.7. Circuit implementation of SAFF Stage2 as slave latch. connected to this branch moving towards logic 0 faster, forcing the other output node to logic 1. So depending on the direction of voltage difference between the differential inputs. At the rising edge of the clock, the pre-charged bistable circuit moves to a certain stable state. Usually further changes in the differential input does not affect this state. So sensing happens in a very narrow time window immediately after the rising edge of the clock Sampling Window The sampling window as to be determined to in order to estimate the metastability. So, a sampling window based technique was implemented. The test bench is shown in the Figure 5.8 [5]. Figure 5.8. Test bench of sampling window technique. We also need to calculate the delay from clock to the outputs. As it is depicted in the Figure 5.9 The delay from clock to the outputs take about ps. This is slightly higher that the value which is presented in the paper [5]. Also due to the symmetry in

69 5.3 Sense Amplifier Flip Flop 55 Figure 5.9. SAFF outputs with a load of 200 ff. the circuit, the crossing of the outputs should be at V DD 2. Therefore from the Figure 5.9, the value seems to around 560 mv which proves the symmetry and also the equal delay of clock to the outputs Simulation of DC Offset Voltage The DC offset voltage occurrence in a comparator is explained in the Section As also described in Section 4.2.9, negative feedback cancellation technique was implemented to find the offset voltage mismatch. A histogram of the offset mismatch is shown in the Figure 5.10 It has µv and 97.7 µv as the mean and the standard deviation. These kind of simulations are time consuming and considerable number of runs have to taken to account in order to achieve at least a standard deviation of 2σ to 2σ which covers most of the cases. As we previously calculated the equations describing the total mismatch variance, we can plug in the results which we obtained for both the inverter delay chain mismatch and offset match. It s value is found to be 523 fs, which does not disturb the worst case propagation delay (t delay ) of 10 ps.

70 56 Implementation, Simulation and Performance Figure Monte Carlo histogram of offset voltage mismatch. 5.4 Pseudo-Thermometer Code Edge Decoder Implementation and Performance The outputs from the sense amplifier flip flops follows a pattern of a Pseudo- Thermometer code. The coded output contains informations such as the rise and fall time of the HCLK or the high frequency signals passing through the chain as in the Figure 5.11 [20]. Figure Timing diagram of TDC core signals [20].

71 5.4 Pseudo-Thermometer Code Edge Decoder 57 The coded output can be converted into binary outputs by a simple priority decoder which searches for one to zero transition and estimates t r values and it s done vice-versa for the t f values. All these timing information are time quantized by the inverter propagation delay. A sample decoder schematic and the full decoder circuit is shown in the following Figures 5.12,5.13. Figure Test bench of pseudo-thermometer decoder. Figure Synthesized circuit of 6-bit pseudo-thermometer decoder.