Characterization and Modeling of SiC Integrated Circuits for Harsh Environment

Transkript

1 DEGREE PROJECT IN INFORMATION AND COMMUNICATION TECHNOLOGY, SECOND CYCLE, 30 CREDITS STOCKHOLM, SWEDEN 2017 Characterization and Modeling of SiC Integrated Circuits for Harsh Environment DAIKI KIMOTO KTH ROYAL INSTITUTE OF TECHNOLOGY SCHOOL OF INFORMATION AND COMMUNICATION TECHNOLOGY

2

3 Karakterisering och Modellering av Integrerade Kretsar i SiC för Extrema Miljöer Sammanfattning Elektronik för extrema miljöer, som kan användas vid hög temperatur, hög strålning och omgivning med frätande gaser, har varit starkt önskvärd vid utforskning av rymden och övervakning av kärnreaktorer. Kiselkarbid (SiC) är en av kandidaterna inom material för extrema miljöer på grund av sin höga temperatur- och höga strålnings-tolerans. Syftet med denna avhandling är att karakterisera 4H-SiC MOSFETar vid hög temperatur och att konstruera SPICE modeller för 4H-SiC MOSFETar. MOSFET-transistorer karakteriserades till 500 C. Med användande av karaktäristik för en 4H-SiC NMOSFET med L/W = 10 m / 50 m, anpassades en SPICE LEVEL 2 kretsmodell. Modellen beskriver DC karakteristiska av 4H- SiC MOSFETar mellan 25ºC och 450ºC. Baserat på SPICE-kretsmodellen simulerades egenskaper för operationsförstärkare och digitala inverterar. Därutöver analyserades driften av pseudo-cmos vid hög temperatur och principen för konstruktion av pseudo-cmos föreslogs. Arean och utbytet (s.k. yield) av pseudo-cmos integrerade kretsar uppskattades och det visar sig att SiC pseudo-cmos integrerade kretsar kan använda mindre area än SiC CMOS integrerade kretsar. Nyckelord Silicon carbide, Extrema Miljöer, Hög tempeatur, Pseudo-CMOS, SPICE kretssimulering, Utbytet uträkning 1

4 Abstract Harsh environment electronics, which can be operated at high-temperature, high-radiation, and corrosive gas environment, has been strongly desired in space exploration and monitoring of nuclear reactors. Silicon Carbide (SiC) is one of the candidates of materials for harsh environment electronics because of its high-temperature and high-radiation tolerance. The objective of this thesis is to characterize 4H-SiC MOSFETs at hightemperature and to construct SPICE models of the 4H-SiC MOSFETs. The MOSFET devices were characterized up to 500ºC. Using the characteristic of a 4H-SiC NMOSFET with L/W = 10 µm/50 µm, a SPICE LEVEL 2 circuit model was constructed. This model describes the DC characteristic of the 4H-SiC MOSFETs in the range of ºC. Based on the SPICE circuit model, the characteristics of operational amplifiers and digital inverters were simulated. Furthermore, the operation of pseudo-cmos at high-temperature was analyzed and the operation principle of pseudo-cmos was suggested. The device area and yield of pseudo-cmos integrated circuits were estimated and it is shown that SiC pseudo-cmos integrated circuits can use less area than SiC CMOS integrated circuits. Keywords Silicon carbide, Harsh environment, High-temperature, Pseudo-CMOS, SPICE circuit simulation, Yield calculation. 2

5 Table of Contents Abstract... 2 Table of Contents... 3 Acknowledgments... 5 Acronyms Introduction Demands for Harsh environment electronics Wide-bandgap Semiconductor for Harsh environment application Scope of Thesis Outline of Thesis SiC properties Crystal structure Electrical property SiC process technology SiC device for integrated circuits Summary Sample preparation NMOS Concepts of device Fabrication flow I-V characteristic Metal-semiconductor contact Type of metal-semiconductor contact Concept of device Transmission Line model Four-terminal contact method Inverter Brief overview of inverter and its family Pseudo-CMOS Tested device Summary Characterization NMOS Metal-semiconductor contact TLM measurement Kelvin pattern Pseudo-CMOS inverter Summary Modeling SPICE Modeling for MOSFETs Modeling method Parameters Benchmark test results Discussion

6 5.6. Summary SiC circuits Operational amplifier (Opamp) Candidate of inverter Operation analysis of pseudo-cmos Simulation condition Discussion of simulation results Design of pseudo-cmos Yield calculation of 4H-SiC integrated circuits Calculation method Calculation result Scaling of pseudo-cmos integrated circuits Summary Conclusions and Future work Reference Appendix A SPICE parameter extraction A.1 Delimitation of modeling A.2 Parameter extraction from MOSFET I-V characteristic A.3 Implementation of SiC MOSFET SPICE model Appendix B SiC operational amplifier with diode-connected loads

7 Acknowledgments This thesis was conducted as my degree project at the department of integrated devices and circuit (EKT), KTH Royal Institute of Technology and this degree project is a part of my double-degree program between KTH and Tohoku University, Japan. First, I appreciate the two supervisors, Prof. Carl-Mikael Zetterling and Assoc. prof. Shin-Ichiro Kuroki, the examiner Prof. Mikael Östling. They gave me insightful discussion about my degree project. Not only in this project, Prof. Carl-Mikael Zetterling and Prof. Mikael Östling gave me insightful knowledges about semiconductor processes and simulations through the nanotechnology program at KTH. The evaluated 4H-SiC devices were fabricated under the collaboration between Hiroshima University in Japan and KTH Royal Institute of Technology. I appreciate the useful discussions about the design and fabrication of 4H-SiC devices. I thank researchers at EKT for discussing about various research about semiconductor devices. As for study at KTH, I appreciate Ms. Malin Hedberg, an international coordinator of double-degree program at school of ICT. She supported me through my exchange study in KTH. I also thank International Exchange division at Tohoku University that supported me for the double-degree program. I thank my supervisors at Tohoku University, Prof. Shigetoshi Sugawa, Assoc. prof. Rihito Kuroda, Prof. Akinobu Teramoto for the encouragement of my studying abroad. I thank my friends I met during my studying abroad. Spending time with my friends is one of the best parts of my studying abroad. Lastly, I appreciate my parents for helping me a lot. Daiki, Stockholm January

8 Acronyms APCVD BHF BJT CMOS IC IGBT JFET MESFET MOS MOSFET NMOS PMOS SPICE VTC Atmospheric Pressure Chemical Vapor Deposition Buffered Hydrogen Fluoride, (BOE: Buffered Oxide Etch) Bipolar Junction Transistor Complementary Metal-Oxide Semiconductor Integrated Circuit Insulated-Gate Bipolar Transistor Junction gate Field-Effect Transistor Metal-Semiconductor Field-Effect Transistor Metal-Oxide-Semiconductor Metal-Oxide-Semiconductor Field-Effect Transistor n-type MOSFET p-type MOSFET Simulation Program with Integrated Circuits Emphasis Voltage Transfer Characteristic 6

9 1. Introduction The objective of this thesis is to characterize and to model 4H-SiC device s operation at high-temperature for further harsh environment electronics. Here, a definition of harsh environment electronics is given and an overview of the electronics are given. In the end of this chapter, the scope and structure of this thesis are explained Demands for Harsh environment electronics Since the transistor was invented, semiconductor devices have been developed dramatically. In integrated circuits (IC), billions of transistors are included in one chip, and Semiconductor devices enable us to handle radiofrequency signals, large amount of data, photon-electron conversion and more. We have cultivated information and communication technology along with the development of semiconductor technology. Nowadays, the functions of semiconductor devices are indispensable in our social life. The industry of semiconductor devices has impact on economical markets due to its large market. For the next application of the semiconductor devices, harsh environment electronics are desired. The harsh environments are defined as hightemperature, high-radiation, high-pressure, and corrosive gas environments, and the harsh environments electronics is a system which can work under the harsh-environments. Next, the applications of the harsh environments, and the issues are explained. Figure 1.1 shows applications at high-temperature and highradiation environment. We can find harsh environments in turbine engine, space exploration, nuclear reactor and so on. 7

10 Temperature (ºC) 1.2 Wide-bandgap Semiconductor for Harsh environment application Turbine engine Harsh-environment electronics Inside of nuclear reactor Cylinder Oil/Gas drilling Automobile Si device SiC device Planetary exploration Space ITER Nuclear reactor monitoring 100 Medical Device Accelerators Radiation exposure (kgy) Fig. 1.1 Application of harsh-environment electronics (Reproduced from [1]). Conventional Si devices can only work in a limited area. In high-temperature environments, conventional silicon (Si) devices cannot be operated, because intrinsic carrier concentration are induced at high temperature owing to its small bandgap, and leakage current from the intrinsic carrier induces failure of the devices. To give actual facts, the inside of the aircraft s engine-room is approximately 315ºC [2]. As for the space-exploration to Venus, the average temperature of atmosphere in Venus is approximately 464ºC [3], and conventional Si devices malfunction in these environments. To operate conventional Si devices at high-temperature, the devices can be kept at safe temperature using an external cooling system. However, the cooling system becomes bulky, and the system-reliability will be degraded. Hence, the harsh-environment electronics itself should be durable at high-temperature. In high-radiation environment, ionizing effect appears in semiconductors and insulators and devices malfunction, for example, bit error in memory device will happen. As for the decommission of Fukushima Daiichi Nuclear Power Plant in Japan, the radiation tolerance should be 150 Gy at minimum [4] Wide-bandgap Semiconductor for Harsh environment application Currently, most integrated devices are fabricated on silicon (Si) substrates. Si has good manufacturability and carrier motility; therefore, Si is adopted in the industry. However, the operating temperature of Si devices is limited because of the bandgap. The intrinsic carrier density of Si can easily exceed the dopant density over 150ºC. Instead of Si, Wide-bandgap semiconductors are preferred for harsh environment electronics. For the high-temperature application, the wide-bandgap semiconductor has advantages such as low 8

11 Chapter 1 Introduction intrinsic carrier concentration, and low leakage current at a p-n junction [5]. The intrinsic carrier electron/hole concentration inherently exists in a semiconductor, and the intrinsic carrier concentration is calculated from Eg ni NC NV exp 2kT, (1.1) where Nc, and Nv are the effective density of states of the conduction band and the valence band respectively, they have dependency of temperature, T 3/2. Eg is the bandgap, and k the Boltzmann constant. Here, the dependency of temperature is larger at the term Eg/2kT than Nc and Nv. Therefore, the intrinsic carrier concentration increases with temperature. In Si, the intrinsic carrier concentration will be over the doping impurities of cm -3 at 300ºC. On the other hand, the wide-bandgap semiconductor has larger Eg (4H-SiC: 3.24 ev, GaN: 3.4 ev) than Si, and the intrinsic carrier concentration at wide-bandgap semiconductor is suppressed, and therefore SiC devices can be operated beyond 600ºC theoretically. As for the leakage current at the p-n junction, the current is: ni D qva/ kt W qva/2kt I pn-leak qani e 1 e 1, (1.2) N D 2 where A is the area of the p-n junction, VA the voltage applied to the diode, ND the n-type doping density, W the width of the junction depletion region at the applied voltage VA, D the hole diffusion constant, and the effective minority carrier lifetime. Here, ni depends on bandgap, and therefore, the leakage current is suppressed using wide-bandgap semiconductor. In addition to the application for harsh environments, the wide-bandgap semiconductor is expected to be used for power devices to decrease energy-loss of power-conversion, because wide-gap semiconductor can reduce onresistance of power MOSFET with its high-blocking voltage and thin drift-layer. However, there is a trade-off between blocking voltage and switching speed, hence MOSFET devices are oriented for high-speed power devices, and insulated gate bipolar-transistor (IGBT) are oriented high voltage power devices. Wide-bandgap semiconductors can realize MOSFETs satisfying both high-voltage and faster switching speed [6]. For the wide-bandgap semiconductor, research has been conducted on crystal properties, epitaxial technique, device processing and so on. As for the candidate of wide-bandgap semiconductor, Silicon Carbide (SiC), Gallium Nitride (GaN) and Diamond (C) have been researched Scope of Thesis The purpose of this thesis is to construct a harsh-environment sensing system durable up to 450ºC. The block diagram of the system is illustrated in Fig The system includes sensors, amplifiers, analog/digital converter, CPU, and memory and so on. The system is suggested by KTH group for Venus exploration [7]. The system is desired to be implemented on a chip, and external cooling system is not needed. Each component is constructed with 4H-SiC transistors. 9

12 1.3 Scope of Thesis Sensor Amplifier ADC ADC CPU I/O ADC ADC: Analog-Digital Converter I/O: Input/Output Memory Fig. 1.2 Harsh-environment sensing system [7]. The entire system is placed in a harsh-environment. A physical value is transduced to electric signal in the sensor, and the small signal from the sensor in the amplifier, the ADC converts the signal to digital values. To realize the system with 4H-SiC circuits, we need to investigate material property of SiC and other related materials and to develop SiC processing technology, model material property/device operation, and we need to optimize device structure, layout of the circuit for each purpose. This technology will be realized when all of requirements are fulfilled. Hiroshima university developed SiC processing technology and the design of device structure, and the device performance at high-temperature and high-radiation were reported in [8] [10]. To develop further 4H-SiC circuits, the device operation at high-temperature should be modeled, and the circuit design of analog/digital circuit are needed based on the model. Furthermore, device area and yield calculation of CPU and memory would be useful to optimize device structure and circuit design. Hence, this thesis focuses on the following works: (1) the characterization of 4H-SiC MOSFETs device in the range of ºC, (2) circuit modeling of 4H-SiC MOSFET and the model oriented for ºC, (3) operational amplifier for analog circuit and inverters for digital circuits based on the circuit model. (4) device area / yield calculation of SiC CPU and memory based on current SiC processing technology. The procedure of this project is shown in Fig In this project, we measured 4H-SiC devices designed and fabricated by Hiroshima University. This group suggested SiC processing technology and Nb/Ni Ohmic contact system, and high-radiation immunity SiC devices have been successfully fabricated [8] [11]. The characterization for NMOSs, metal-semiconductor contacts, and pseudo-cmos inverter at high-temperature was conducted in the collaboration with Hiroshima University and KTH. Secondly, Circuit level modeling was performed. A circuit simulation model (SPICE MOSFET LEVEL 2) was constructed based on the measurement results [8]. The circuit model can be utilized in the range of ºC. Thirdly, 4H-SiC circuits of operational 10

13 Chapter 1 Introduction amplifier and inverter were simulated with the constructed circuit model. Device fabrication [8-11] Characterization Modeling Design of circuit MOSFET, Ohmic-contact, Pseudo-CMOS Circuit model SPICE Level2 MOSFET Pseudo-CMOS inverter, Pseudo-nMOS inverter, Opamp with active load. Device area/yields calculation Fig. 1.3 Procedure of this project Outline of Thesis CPU, Memory This thesis is constructed as follows: In chapter 2, the crystal and electrical property of SiC, SiC processing technology, and SiC devices for integrated circuits are explained. In chapter 3, the fabrication process and the structure of the 4H-SiC MOSFET are explained based on [8] [10]. The design concepts of Nb/Ni metal-semiconductor contact, pseudo-cmos inverter are illustrated. In chapter 4, the electrical properties of the devices at high-temperature are described, i.e. the input characteristic (IDS-VGS characteristic) and the output characteristic (IDS-VDS characteristic) at high temperature condition are described. In chapter 5, the circuit model for 4H-SiC MOSFET and the method of constructing the circuit model is explained. In chapter 6, the simulation result of an operational amplifier based on the new circuit model, and the operation of pseudo-cmos is analyzed with the circuit model, and pseudo- CMOS and CMOS integrated circuit is compared based on the device area and yield calculation. In chapter 7, the conclusion and the future work of this thesis is explained. In addition to them, the detail of our circuit model is explained in Appendix A. 11

14 2. SiC properties In this chapter, the properties of SiC, in terms of crystal and electrical property of SiC, and SiC device processing are described. Furthermore, the classification of SiC devices for integrated circuits is explained Crystal structure Silicon carbide (SiC) is a compound semiconductor consisting of Silicon (Si) and Carbon (C). From stoichiometric aspect, the crystal is composed of 50 % of Si and 50 % of C. Each atom in SiC has covalent bond of Si-C, which has much higher binding energy (4.6 ev) than the Si-Si bond (1.8 ev). This high binding energy contributes the marked electrical and mechanical properties of SiC. There are several crystal structures in SiC because of the stacking sequence of Si atoms and C atoms. the possible sites of the atoms are illustrated in Fig If one layer is aligned as A, the next layers can be aligned in two ways, B and C above A. Side view of each stacking sequences are illustrated in Fig The stacking sequences are classified as follows: 3C-SiC; ABC, 4H-SiC; ABCB, 6H- SiC; ABCACB and 3C-SiC has cubic crystal and 4H- and 6H- are hexagonal crystal as illustrated in Fig The annotation, 3C-, 4H-, 6H- means the number of repeated stacking sequences and the structure of crystal (cubic or hexagonal) respectively. More ways of stacking in SiC can exist and not all of them have been found. For the notation of crystal planes in hexagonal crystal, Miller indices are used as shown in Fig In hexagonal or rhombohedral structure, the (0001) Si is called Si face because the surface is terminated by Si atoms, whereas the (0001) C surface is called C face because the surface is terminated with C atoms. B B B B B C C C C C a 1 [0001] a 3 a 2 Fig. 2.1 Occupation sites (A, B, and C) in the hexagonal close-packed system. The dashed-line circle indicates the A sites [12]. 12

15 Chapter 2. SiC properties [111] C atom Si atom (a) C B A C B A Å (b) [0001] Fig. 2.2 Schematic structures of popular SiC polytypes; (a) 3C-SiC, (b) 4H-SiC, and (c) 6H-SiC [12], [13]. C B A B C B A Å (c) A C B A B C A C B A a 3 c a 1 a 2 a 3 a 1 a 2 (a) Cubic SiC (b) Hexagonal SiC Fig. 2.3 Primitive cells and fundamental translation vectors of (a) cubic (3C) SiC and (b) hexagonal SiC [12]. (0001)Si Si face Fig. 2.4 Definition of several major planes in a hexagonal SiC polytype [12] Electrical property (1100) M face a 3 c a 1 a 2 (1120) A face (0001)C C face One of the advantages of SiC is its wide-bandgap, which contributes highbreakdown voltage, operation at high-temperature, and tolerance to high- 13

16 2.3 SiC process technology radiation. SiC has high-thermal conductivity. 3C-, 4H-, 6H-SiC are indirect band-gap semiconductors and the band-gap narrows with increasing temperature. Table I shows electrical properties of SiC and other semiconductor materials. The electron mobility in SiC is anisotropic, and the electron mobility of 6H-SiC is more anisotropic than 4H-SiC. This is one of the reason why 6H-SiC is not adopted in the industry. The thermal conductivity of SiC is higher than Si. This property would be useful for high-temperature operation. In 3C- and 4H-SiC, the electron/hole mobility are much more unbalanced than Si. Therefore, the size ratio of CMOS would be 5:1 in PMOS and NMOS respectively [14]. Table I Major physical properties of common SiC polytypes at room temperature [13], [15]. Si 3C-SiC 4H-SiC 6H-SiC GaAs Diamond Bandgap E g (ev) Breakdown field EBD (MV/cm) Electron mobility μe (cm 2 /V s) * μe (cm 2 /V s) * Hole mobility μp (cm 2 /V s) Dielectric constant κ Thermal conductivity K (W/cm K) *1 perpendicular to c-axis, *2 parallel to c-axis 2.3. SiC process technology The SiC processing is still in development and the processing technology is not as mature as Si devices. It is considered that SiC processing needs hightemperature due to its strong covalent bond and new equipment may be needed for the processing. In the bulk growth technique for SiC, seeded sublimation (or Modified Lely) is mainly used. For other techniques, high-temperature chemical vapor deposition, and solution growth are also developed. The polytype of SiC can be controlled by temperature and epitaxial techniques. In the sublimation growth, micropipe and threading screw dislocations usually appear, which should be decreased. The sublimation growth technique is the mature technique in those and other two techniques are developing. Now, 150 mm-diameter SiC wafer is available commercially. In the epitaxial growth technique for SiC, chemical vapor deposition (CVD) is 14

17 Chapter 2. SiC properties usually used for a hexagonal SiC polytype on off-axis SiC (0001). Monosilane (SiH4) and propane (C3H8) or ethylene (C2H4) are used for precursors. The typical growth temperature and growth rate are ºC and 3-15 m h -1 respectively. On the epitaxial layer, the surface morphological defects are observed such as carrot defects and triangular defects. To obtain good morphology and homo-type, SiC 4º off-axis substrates are used. For device fabrication, thermal oxidation can be conducted in SiC, Metal-Oxide Semiconductor (MOS) devices have been researched a lot. Because of the widebandgap, SiC MOS device can be employed in high-voltage device. However, High interface state density at the oxide is one of the problems in SiC MOS devices. Because of the high-interface density, the channel mobility is suppressed under 10 % of the bulk mobility, which means most of the carriers at the channel are trapped or scattered by the interface between semiconductor and oxide. To improve the carrier mobility, post-oxidation annealing using nitrogen-containing gas such as nitrogen monoxide (NO), nitrous oxide (N2O), ammonia (NH3) has been tried [16]. The device performance is affected by defects in SiC bulk and epitaxial layer. Main type of defects by stacking faults are micropipes, threading screw dislocations (TSDs), threading edge dislocations (TEDs) and basal plane dislocations (BPDs). If there are defects in the substrate, these defects may be replicated in epitaxial layer as well [12] SiC device for integrated circuits Discrete SiC devices have been commercialized such as SiC Schottky barrier diodes and MOSFETs. These SiC devices are applied to power electronics for decreasing power converting loss. For SiC-integrated circuits, research has been conducted on different type of devices to achieve high integrity, high operation temperature, long stable operation time and so on. Although MOSFET has great advantages because of its low power dissipation and easiness to fabricate, the oxide on SiC has poor electrical properties and it has large amount of interface states, this is one of the obstacles of the development. KTH Royal Institute of Technology focuses on SiC bipolar technology, and they fabricated operational amplifier durable up to at 450ºC [17] and components for digital circuits were also fabricated [18]. Purdue University also fabricated BJT devices [19]. IMB- CNM in Spain fabricated logic circuitry such as master-slave data flip-flop, data reset flip-flop using 4H-SiC MESFET technology [20], [21]. NASA Glenn research center and Case Western Reserve University fabricated differential amplifiers based on 6H-SiC junction effect field transistor (JFETs), and they confirmed stabilities for 6519 hours at 500ºC operation testing [22]. Hiroshima University has fabricated 4H-SiC MOSFETs devices and tolerance to high-temperature and high-radiation were reported [8], [9], [23]. Raytheon UK has fabricated CMOS devices [24], [25] Summary In this chapter, crystal, and electrical property of SiC were overviewed. SiC has several polytypes and each polytype has different electrical properties. The bandgap and thermal conductivity of SiC is larger than Si. There are some 15

18 2.5 Summary difficulties in SiC processing, especially in terms of high-temperature processing. The processing technology is actively discussed in both industry and academia. In MOS devices, the interface state density of SiC MOS is a challenging issue, which is considered as a reason of the low channel mobility of SiC MOSFETs. Although SiC processing technology is still on development, the components for IC were designed and fabricated and its performance at high-temperature, highradiation were reported in research publications. 16

19 3. Sample preparation In this chapter, the design concept and process flow of 4H-SiC MOS capacitors, MOSFETs, and metal-semiconductor contacts are explained. Moreover, the characterization methods of these devices are explained. For digital circuit application, the pseudo-cmos inverter was also fabricated using MOSFETs. The principle of operation is explained. These explanation are based on [8] [10] NMOS Concepts of device These points are considered for the fabrication: (1) The doping density is determined with device simulator, Sentaurus to set the threshold voltage of 3.0 V. (2) niobium (Nb)/nickel (Ni) system is deposited for metal-semiconductor contact to decrease contact resistivity. (3) nitrogen (N2) annealing for oxide was not conducted, though it is reported that the annealing improves the carrier mobility. The reason for not conducting the annealing is to avoid the degradation of MOSFET at high-temperature operation Fabrication flow The fabrication process of 4H-SiC devices is described in Fig. 3.1, 4H-SiC epitaxial layer was deposited on a 4H-SiC n-type (0001) 4º-off substrate. The epitaxial layer was 3 m thickness. The silicon dioxide was deposited using an atomic pressure chemical vapor deposition (APCVD), and was etched to form hard mask. To form S/D region, arsenic (As) ion was implanted (500ºC, cm -3, 70 nm-depth Box-profile). Subsequently, a carbon-cap was deposited to protect the surface from degradation caused during the annealing. The annealing was conducted at a temperature of 1800ºC to activate the dopants. For the gate oxide, silicon oxide was formed at a temperature of 1150ºC with dry thermal oxidation. The Nb/Ni metal contact was deposited above the S/D region. After the deposition, the silicidation was conducted at a temperature of 950ºC. Aluminum (Al) was deposited for the gate electrode. SiO2 was deposited for the interlayer dielectrics. Al contact pad was formed. The schematic structure of the MOSFET is illustrated in Fig

20 3.1. NMOS 1. SiO 2 dummy-gate deposition APCVD, thickness 400 nm 2. Dummy-gate lithography 3. SiO 2 dummy-gate wet-etching BHF 4. Ion-implantation 5. SiO 2 dummy-gate removing BHF 6. Carbon-cap deposition 7. Impurity-activation annealing 1800 ºC, 3 min 8. Carbon cap removal 9. Dry thermal oxidation 1150 ºC, t ox = 10, 20 nm 10. Photo-resist deposition HMDS, ip3300 (17 cp) 11. Mask-less exposure Exposure: 130 mj/cm2 Development: PB, 110 ºC, 90 sec; SD-1, 90 sec Cleaning: H 2 O, 3 min; PB, 130 ºC, 2 min 12. Gate-SiO 2 wet-etching BHF 13. S/D Ohmic contact deposition Nb/Ni = 50/50 nm 14. S/D region Lift-off Acetone cleaning 15. S/D Silicidation 900 ºC, 5 min 16. Gate metal deposition Al, 200nm 17. Photo-resist deposition HMDS, ip3300 (17cp) 18. Mask-less exposure Exposure: 130 mj/cm2 Development: PB, 110 ºC, 90 sec; SD-1, 90 sec Cleaning: H 2 O, 3 min; PB, 130 ºC, 2 min 19. Al etching H 3 PO 4 / HNO 3 / CH 3 COOH 20. Photoresist removal Acetone cleaning Fig. 3.1 Process flow of 4H-SiC NMOS [8] [10]. 21. SiO 2 Interlayer dielectric deposition APCVD, SiO 2 : 300 nm 22. Photo-resist deposition HMDS, ip3300 (17 cp) 23.Maskless exposure Exposure: 130 mj/cm2 Development: PB, 110 ºC, 90 sec; SD-1, 90 sec Cleaning: H 2 O, 3 min; PB, 130 ºC, 2 min 24 SiO 2 Interlayer dielectric Wet-etching BHF 25. Photo-resist removing Acetone cleaning 26. Metal pad deposition Al, 400 nm 27. Photoresist deposition HMDS, ip3300 (17 cp) 28. Mask-less exposure Exposure: 130 mj/cm2 Development: PB, 110 ºC, 90 sec; SD-1, 90 sec Cleaning: H 2 O, 3 min; PB, 130 ºC, 2 min 29. Metal pad etching H 3 PO 4 / HNO 3 / CH 3 COOH 30. Photo-resist removing Acetone cleaning BHF: Buffered Hydrogen Fluoride, 50% hydrogen fluoride and 40% NH 4 PB: Pre-Baking HMDS: hexamethyldisilazane IP3300: i-line Positive photoresist (Tokyo Ohka Kogyo Co.) SD-1: Developing fluid, N(CH 3 )4OH (Tokuyama Co.) 18

21 Chapter 3. Sample preparation H-SiC 2, Source/Drain Carbon cap Photoresist 4 SiO Al metal Ni Nb Nb/Ni alloy Fig. 3.1 Process flow of 4H-SiC NMOS [8] [10].(Continued.) 19

22 3.1. NMOS L/W = 5 μm /1500 μm Al Gate Source Dry- SiO 2 Nb/Ni Drain t ox = 20 nm N + (As) BOX (Depth: 70nm) N D = cm -3 t epi = 3 μm Fig. 3.2 Schematic structure of 4H-SiC NMOS. This structure was fabricated on n-type 4H-SiC (1000) 4º -off substrate [8] [10] I-V characteristic p - epitaxial layer, N A = cm -3 (Cree) The operation mode of MOSFET depends on gate-voltage and drain-source voltage. The voltage of substrate can be also changed to manipulate the threshold voltage of MOSFET. The behavior of MOSFET can be seen in I-V characteristic The MOSFET I-V characteristic is derived from charge-sheet model. The derivation of these equations refers to the literature [26]. The drain current of MOSFET IDS is calculated from: W V DS I DS eff COX VGS VFB 2 p VDS VDS VBS 2 p V BS 2 p, (3.1) L 2 3 where eff is effective mobility, C OX oxide capacitance per unit area, W MOSFET width, L MOSFET length, VGS gate-source voltage, VFB flat-band voltage, 2 p difference between Fermi potential and intrinsic potential, VDS drain-source voltage, body effect, and VBS body voltage. When the drain-source voltage is small, the drain-source current IDS is W 4 SiqNa B I DS eff COX VGS V fb 2 B VDS L C OX, (3.2) W eff COX VGS Vt VDS L where Vt is threshold voltage, 4 SiqNa B Vt Vfb 2 B. (3.3) COX When VDS > VGS -VTH, the IDS is W m 2 I DS eff COX ( VGS Vt ) VDS VDS L 2, (3.4) where 20

23 Chapter 3. Sample preparation SiqNa /4 B m 1. (3.5) COX IDS increases until a saturation condition, and when saturation condition, V V ( V V ) / m is satisfied, IDS becomes DS dsat GS t 2 W ( VGS Vt ) I DS Idsat eff COX. (3.6) L 2 m 3.2. Metal-semiconductor contact Type of metal-semiconductor contact Metal-semiconductor contacts can be found in source-drain region in MOSFET and back-side contact. Low-voltage drop and no rectifying effect is desired in metal-semiconductor contacts. Metal semiconductor contacts are classified in two types in terms of its electrical property, Ohmic contacts and Schottky contacts. The type of contact is determined by the difference of the work function between a metal and a semiconductor. The band-diagram of Ohmic contacts and Schottky contacts are illustrated in Fig In Ohmic contacts, there is no rectifying effect between metal and semiconductor. On the other hand, there is a barrier from metal to semiconductor in Schottky contacts, which makes rectifying effect. Therefore, the I-V characteristic of the contacts becomes like Fig Φ M Φ SC < 0 Φ M Φ SC > 0 E C E F E i E V Φ B E V E F E i Metal n- semiconductor (a) Ohmic contact Metal n- semiconductor (b) Schottky contact Fig. 3.3 Band-diagram of metal-semiconductor (n-type) contacts, (a) Ohmic contacts, and (b) Schottky contacts. E C 21

24 3.2. Metal-semiconductor contact I I V V (a) Ohmic contact Fig. 3.4 I-V characteristic of metal-semiconductor contacts, (a) Ohmic contacts, and (b) Schottky contacts. To make Ohmic contacts, MS - SC is negative for n-type semiconductors and positive for p-type semiconductor. To eliminate rectifying effect in Schottky barrier contacts, a high-doped semiconductor is employed to narrow the space charge region, and therefore field emission happens at the barrier and the rectifying effect can be ignored Concept of device In SiC devices, the method to gain low Ohmic contacts has been actively discussed. Carbon atoms are inherently contained in SiC, and the existence carbon atoms affects the property of the Ohmic contact. As reported in [11], a carbon agglomeration in a conventional nickel silicon (Ni/Si) are appeared at the contact, and the contact resistivity is increased. [11] introduced niobium and nickel (Nb/Ni) alloy for the silicide to avoid the carbon agglomeration, and the contact resistivity was decreased. The measured device was fabricated with the Nb/Ni alloy [8] [10] Transmission Line model For a characterization of the metal-semiconductor contacts, Transmission Line Model (TLM) is widely used [27]. The contact is evaluated as contact resistivity. Figure 3.5 illustrates the cross section of the contact and semiconductor layer with the transmission line. Between the contact metal and the semiconductor layer, there would be an interface layer, which is related to G dx as depicted in Fig. 3.5(b). RSH is the sheet resistance of the semiconductor, which is related to R dx. The transmission line equations of this system are V ( x) V cosh x I Z sinh x, (3.7) 1 1 (b) Schottky contact V1 I( x) I1 cosh x sinh x, (3.8) Z where is the propagation constant, Z the characteristic impedance, V1 and I1 the voltage and current at the node 1 in Fig. 3.6, respectively. In DC operation, the 22

25 Chapter 3. Sample preparation equations can be written as x x v( x) v cosh( ) i Z 'sinh( ) L, (3.9) i x 1 1 LT 1 ( ) i1 cosh( ) sinh( ) LT Z ' LT T x v x, (3.10) where LT is the transfer length, where the voltage v(0) decrease in magnitude by 1/e. The expression of LT is L C T. (3.11) RSH the characteristic impedance Z is 1 Z R SH C. (3.12) W (a) Contact metal Interface layer ρ c Semiconductor layer R s (b) v 1 G dx C dx v 2 R dx i 1 i 2 Fig. 3.5 Transmission line model (TLM), (a) cross section of contact metal and semiconductor, and (b) transmission line [28]. x 23

26 3.2. Metal-semiconductor contact Contact Semiconductor W L d 1 d 2 d 3 Fig. 3.6 TLM test pattern. Each metal is aligned with different spacings d1, d2, d3... Contact V A d I R T = V/I R 2R R T C S R C R C Semiconductor R S (a) Circuit model Fig. 3.7 Model of two metal-semiconductor contacts. (a) circuit model of TLM test pattern, and (b) resistance of TLM pattern versus distance between the contacts. To interpret the metal-semiconductor contact measurements, the contact resistivity, C ( cm 2 ) is useful. The contact resistivity is measured in a test pattern, where multiple contacts are located sequentially as depicted in Fig The resistance between two metal contacts are measured with the two-terminal method at each two metal contacts. As shown in Fig. 3.7(a), the resistance RT ( ) consists of two resistances, the resistance of the semiconductor RS ( ), and the resistance under the metal contact RC ( ). Plotting RT as depicted in Fig. 3.7(b), RC is gained from the intercept across y-axis, and LT is gained from the intercept across x-axis. The equation of RT is d x 2R SK R SH L T (b) R T d d 24

27 Chapter 3. Sample preparation RSK LT RSHd R T 2R C R S 2 W W, (3.13) where RSH ( /sq.) is the sheet resistance of semiconductor, RSK ( /sq.) that of the semiconductor under the contact. Assuming RSK RSH, the contact resistivity is calculated from R SK LT 2 2 C RC LTW LTW RSK LT RSH LT. (3.14) W Four-terminal contact method In the TLM measurement, the contact resistivity and sheet resistance can be known simultaneously; however, the assumption that the sheet resistance under the metal contact is equal to the other sheet resistance would induce an error of calculation, and therefore four-terminal contact method is preferred to gain precise values. In this method, there is high-impedance in a voltmeter and little current flows into the voltmeter, and hence the voltage drop in the sheet resistance and metal pad can be ignored [27]. W I bias N-layer A c I L N-layer I Ibias V V (a) Contact resistance (b) Sheet resistance Fig. 3.8 Four-terminal contact/sheet resistance test pattern. (a) the pattern for contact resistance, and (b) test pattern for sheet resistance. From the measurement, the contact resistance is calculated from 25

28 3.3. Inverter V RC, (3.15) I where V is the voltage of meter and I the bias current. The contact resistivity C is C RA C C, (3.16) where A c is the area of the contact. The sheet resistance RSH is WV RSH, (3.17) L I where W is the width of the semiconductor, and L the length of the semiconductor Inverter Brief overview of inverter and its family The ideal property of inverter is shown in Fig The inverter can transfer 1 -state to 0 -state in terms of a voltage. Voltage transfer characteristic is like a step function and the power dissipation of inverter should be minimized for application. The inverter is an important building block for logic circuits. IN OUT (a) Symbol of inverter IN OUT Output voltage V OUT V M Input voltage V in (b) Truth table (c) Voltage transfer characteristic of inverter Fig. 3.9 Property of inverter, (a) symbol of inverter, (b) truth table, and (c) voltage transfer characteristic (VTC). The classification of inverters is illustrated in Fig Figure. 3.10(a) is the simplest idea to implement inverter using one resistor and one switch. Based on this idea, the NMOS inverter (Fig. 3.10(b)) and pseudo-nmos inverter (Fig. 3.10(c)) were invented. In pseudo-nmos, the pull-up transistor M1 is always operated in saturation mode, and the pull-down transistor M2 works in triode 26

29 Chapter 3. Sample preparation mode at 0 state and therefore the voltage at 0 state VOL is calculated from 1 Vtp ( W / L) p 1 VOL ID 1rds 2, (3.18) 2 n ( VDD Vtn )( W / L) 2 where p and n are the carrier mobility of PMOS and NMOS respectively, Vtp and Vtn are threshold voltages of PMOS and NMOS respectively. (W/L) is the aspect ratio of the MOSFET. However, NMOS inverter and pseudo-nmos are not adopted in Si IC because of its high-power dissipation. On the other hand, complementary metal-oxide-semiconductor (CMOS) inverter has low-power dissipation, and thus it is widely used. The CMOS inverter is composed of a PMOS and a NMOS as illustrated in Fig. 3.10(d). When the Vin is 0 V, the PMOS (M1) is turned on and the Vout is VDD, whereas if the Vin is VDD, the NMOS (M2) is turned on and the Vout is 0 V. Moreover, there is no static current, which flows from V DD to GND only the transient current in switching [26]. Hence, CMOS inverter has low power dissipation. The size of PMOS and NMOS is optimized to balance the drain current of each MOSFET. In Si technology, a size ratio of 1:2 is needed for NMOS and PMOS respectively; however, the technology of SiC MOSFET is not as mature as Si technology, and the carrier mobility of PMOS is 2 or 3 times lower than NMOS. Therefore, the configuration of CMOS would be 1:5, which causes large device area and large input capacitance correspondingly [14]. 2 27

30 3.3. Inverter V DD V DD R M1 V out V out S V in M2 (a) Basic idea of inverter (b) nmos (Active load) M1 V DD M1 V DD V out V in V out V in M2 M2 (c) Pseudo-nMOS (d) CMOS Fig Circuit diagram of inverter family (a) Basic idea of inverter (b) NMOS inverter, the load is diode-connected transistor instead of resistance, (c) pseudo- NMOS, the pull-up transistor is normally-on PMOS. (d) CMOS, PMOS and NMOS is configurated to balance the drain current Pseudo-CMOS To achieve inverters with monotype transistors, pseudo-cmos is suggested. The circuit diagram of pseudo-d and pseudo-e are illustrated in Fig Pseudo- CMOS is consisted of four monotype MOSFETs. This idea is firstly found in thin film transistors (TFTs) to implement inverters with monotype transistors [29], [30]. This inverter can be viewed as two stage inverters. In pseudo-d CMOS, the first inverter has zero-vgs load which is a transistor whose gate and source is shorted. Zero-VGS load inverter is also found in organic TFTs and the operation principle is explained in [31], [32]. In pseudo-e CMOS, the first inverter has an active load. This circuit is operated with two bias voltages, VSS and VDD. VDD 28

31 Chapter 3. Sample preparation determines the voltage at high-state, and voltage transfer characteristic can be modulated with VSS. The principle of the operation of pseudo-cmos is not analyzed quantitatively; however, the qualitative interpretation of pseudo-d type inverter can be found in [1]: the gate-width of M3 is usually designed smaller than M1, M2 and M4. When Vin = 0, the two transistors, M1 and M3 can be regarded as a series resistance. The voltage drop at M3 is larger than M1 because gate-width of M3 is smaller than M1, and the drain of M3 is connected to the gate of M1, therefore, M1 turns on. Subsequently, VSS is applied in the gate of M2 and the M2 turns on and therefore, VOUT is high. When Vin = 1, the M4 turns on and the Vout becomes off-state, and this circuit works as an inverter. V SS V DD V SS V DD M1 M2 M2 V out M1 V out V in M3 M4 V in M3 M4 (a) Pseudo-D (b) Pseudo-E Fig Circuit diagram of pseudo CMOS inverter, (a) pseudo-d type, and (b) pseudo-e type. The difference of two pseudo-cmos is the connection of M1 gate and the configuration of M1 and M2. In pseudo-d type, W1/W3 < 1 whereas W1/W3 > 1 in pseudo-e type [30] Tested device Pseudo-D type was fabricated with 4H-SiC NMOS in the previous works [9], [23]. The fabrication process of NMOS followed Fig The channel length was fixed to 5 μm. M1, M2 and M4 had a width of 5000 μm and M3 had 1500 μm width. This device was measured up to 200ºC [9]. To clarify the operation at hightemperature, voltage transfer characteristics at ºC were measured Summary The concept of 4H-SiC MOS devices, which are designed and fabricated at Hiroshima University, are explained. In the devices, Nb/Ni Ohmic contact is employed in order to improve metal-semiconductor contact. Pseudo-CMOS inverter was employed in 4H-SiC devices for digital circuits, and the inverter is composed of monotype transistors. 29

32 4. Characterization In this chapter, the measurement results at high-temperature of the MOSFET I-V characteristic, contact resistivity of Nb/Ni silicide contact, sheet resistance of n-type box layer, and voltage transfer characteristic of pseudo-cmos inverter are described NMOS The measured I DS -V GS characteristic is depicted in Fig. 4.1 and I DS -V DS characteristic is depicted in Fig From the characteristic, we can find this device has transistor-operation. Moreover, (1) the threshold voltage decreased with temperature. The relationship between threshold voltage and temperature was extracted from IDS-VGS, which is shown in Fig (2) the drain current increased with temperature. The relationship between drain current and temperature was extracted from IDS-VDS, which is shown in Fig the threshold voltage was shifted by 1 V from 25ºC to 500ºC. The drain current at VGS = 5 V. VDS = 3 V increased 3 orders of magnitude from 25ºC to 500ºC. These characteristic is similar to the 4H-SiC MOSFET (L/W = 10/50 m) as reported in [8]. However, there is unexpected current at the tail of IDS-VDS curve in Fig. 4.2(a) and (b). The amount of the tail current is comparably small at the characteristic at the characteristic of Fig. 4.2(c) and (d), so that the tail current was not observed. The reason of this tail current is still unknown; however, the geometry of the MOSFET is larger than [8], so that the current induced by defects would be observed. Drain current I DS (A) L/W = 5 μm/ 1500 μm t ox = 20 nm T = ºC V DS = 0.5 V Gate voltage V GS (V) Fig. 4.1 IDS-VGS characteristic of 4H-SiC NMOS. The direction of the arrow indicates the increase of temperature. T 30

33 Chapter 4. Characterization Drain current I DS (A) 10-7 Drain current I DS (A) L/W = 5 μm/1500 μm t ox = 20 nm 25 ºC V GS = 5 V V GS = 4 V V GS = 3 V Drain-source voltage V DS (V) L/W = 5 μm/1500 μm t ox = 20 nm 300 ºC V GS = 5 V V GS = 4 V V GS = 3 V Drain-source voltage V DS (V) Drain current I DS (A) L/W = 5 μm/1500 μm t ox = 20 nm 150 ºC V GS = 5 V V GS = 4 V V GS = 3 V Drain-source voltage V DS (V) (a) 25 ºC (b) 150 ºC Drain current I DS (A) L/W = 5 μm/1500 μm t ox = 20 nm 500 ºC V GS = 5 V V GS = 4 V V GS = 3 V Drain-source voltage V DS (V) (c) 300 ºC (d) 500 ºC Fig. 4.2 IDS-VDS characteristic of 4H-SiC NMOS. 31

34 Drain current I DS (A) Threshold Voltage V TH (V) 4.1. NMOS L/W = 5 μm/ 1500 μm t ox = 20 nm Temperature T (ºC) Fig. 4.3 Temperature dependence of threshold voltage of 4H-SiC NMOS. This characteristic was extracted from IDS-VGS characteristic in Fig E E E E E L/W =5 μm/1500 μm t ox = 20 nm V GS = 5 V V DS = 3 V Temperature T (ºC) Fig. 4.4 Temperature dependence of drain-current at VGS = 5 V and VDS = 3 V. This characteristic was extracted from IDS-VDS characteristic in Fig

35 Current (ma) Resistance R T (Ω) Chapter 4. Characterization 4.2. Metal-semiconductor contact TLM measurement The I-V characteristics at each contact interval are depicted in Fig. 4.5 (a). The resistance calculated from the slope of the I-V curve is depicted in Fig. 4.5 (b) Ni/Nb L/W = 0.02/0.01 mm N D = cm -3 T = 25 ºC d Voltage (V) (a) I-V characteristic y = 2.83x (b) R T d Fig. 4.5 Measurement result of TLM test pattern (a) I-V characteristics at 25ºC, (b) resistance contact interval characteristics at 25ºC. Based on RT-d characteristic at each temperature, transfer length, sheet resistance of semiconductor, and contact resistivity were calculated. Figure 4.6 shows temperature dependence of these parameters. The transfer length and contact resistivity decreased with temperature Ni/Nb L/W = 0.02/0.01 mm N D = cm -3 T = 25 ºC Contact interval d (μm) 33

36 4.2. Metal-semiconductor contact (a) Transfer length Transfer Length L T (μm) (Ω/sq.) Ni/Nb L/W = 0.02/0.01 mm N D = cm Temperature (ºC) 6.0 Sheet resistance R SH Ni/Nb L/W = 0.02/0.01 mm N D = cm Temperature (ºC) (b) Sheet resistance Contact resistivity ρ c (Ωcm 2 ) Ni/Nb L/W = 0.02/0.01 mm N D = cm Temperature (ºC) (c) Contact resistivity Fig. 4.6 Measurement result of TLM pattern. (a) transfer length versus temperature, (b) sheet resistance of semiconductor versus temperature, and (c) contact resistivity versus temperature Kelvin pattern The measurement result from the four-terminal contact method is depicted in Fig As for the contact resistivity, the order of magnitude is -3 and it is about 2 times to Fig. 4.6(c), and it also decreased with temperature. On the other hand, the sheet resistance increased with temperature, which is opposite results from Fig. 4.6(b). It is because that the calculation for TLM has an assumption of RSH = RSK. On the other hand, sheet resistance is measured directly in Kelvin pattern, and therefore, Fig. 4.7 (b) would be more accurate results than Fig. 4.6 (b). From the view point of carrier dynamics, the increase of sheet resistance would indicate that the scattering by phonon strongly affected the carrier transfer. From the measurement results, the decrease of contact resistivity and increase of sheet resistance with temperature should be taken account into modeling. 34

37 Chapter 4. Characterization Temperature (ºC) (a) Contact resistivity (Ω/sq.) Contact resistivity ρ c (Ωcm 2 ) Fig. 4.7 Measurement result of four terminal contact method(a) contact resistance versus temperature, (b) sheet resistance versus temperature Pseudo-CMOS inverter A c = 25 μm 2 y = x Sheet resistance R SH y = x (b) Sheet resistance Figure 4.8 shows the voltage transfer characteristic of a pseudo-cmos inverter in the range of ºC. the relationship between the slope and temperature is depicted in Fig The maximum slope of inverter increased with temperature until 350ºC, and the voltage swing increased until 100ºC and saturated in the range of ºC. However, the maximum gain and voltage swing started to decrease from 400ºC. The decrease would not be caused from the operation limit of SiC, and the defects at any of transistor would be triggered by heat. To clarify the phenomenon, the same measurement should be conducted on other pseudo-cmos inverters N D = cm -3 depth = 70 nm L/W = 230/25 μm Temperature (ºC) 35

38 Gain (Times) Voltage swing (V) Output voltage V out (V) 4.3. Pseudo-CMOS inverter ºC 50ºC 100ºC 150ºC 200ºC 250ºC 300ºC 350ºC 400ºC 450ºC Input voltage V in (V) Fig. 4.8 Voltage transfer characteristic of pseudo-cmos inverter (dual sweeps) Pseudo-CMOS Temperature T (ºC) Fig. 4.9 Maximum slope of VTC (Gmax) and voltage swing at pseudo-cmos inverter versus temperature. 36

39 Chapter 4. Characterization 4.4. Summary We characterized MOSFET I-V characteristic, metal-semiconductor contact resistivity, and voltage transfer characteristic of pseudo-cmos. 4H-SiC NMOS with L/W = 5 m/1500 m was operated in the range of ºC, However, there was anomalous increase of drain current at VDS > 7 V at the IDS-VDS characteristic. The voltage transfer characteristic of the pseudo-cmos inverter showed that the slope of VTC increased with temperature, however there was decrease of maximum output voltage at 400ºC and 450ºC. 37

40 5. Modeling Circuit modeling is effective to design more complicated 4H-SiC circuits without any costly and time-consuming fabrication. In this thesis, the SPICE2 MOSFET level2 model for 4H-SiC MOSFET was constructed in the range of ºC using the measurement result in Chapter 4. In this chapter, the method of the parameter extraction from 4H-SiC NMOS, and the parameter list is described SPICE Modeling for MOSFETs The circuit simulation can show the operation in advance and it has merit of less time and cost. Simulation Program with Integrated Circuits Emphasis (SPICE) is one of the analog circuit simulator, and SPICE was firstly suggested by the group of University of California Berkeley [33], [34]. As transistors are scaled down, the SPICE model has been developed as well, and plenty of SPICE models can be found. SPICE2 model is an elementary MOSFET circuit model and it is based on a physical model. In TABLE II, the parameter of SPICE 2 model (level1 3) are tabulated. In SPICE2, 39 parameters are employed at maximum. Apart from the SPICE2 model, the Berkeley Short-Channel IGFET Model (BSIM) is oriented for small-geometry MOSFET and the geometry of 1 m and the thickness of 15 nm can be simulated, and 79 parameters are employed for BSIM1 model. BSIM2 and BSIM3 were also introduced for further modeling. These models take account of the doping profile, the charge at bulk, noise. Moreover, The SPICE model for other device structure and semiconductor has been employed, such as silicon on insulator (SOI) MOSFET and FinFET. SPICE Simulation for the SiC devices are found in several works. The 4H-SiC power MOSFET up to 200ºC operation was simulated in [35]. SPICE modeling for JFET is employed for up to 500ºC [36]. Device performance depends on device structures and processing techniques; hence we need to choose a proper circuit model, and to set model parameters Modeling method To conduct SPICE simulations, we used SPICE2 MOSFET LEVEL2 model. It is because the geometry of the MOSFET is relatively large (L = 10 m, tox = 20 nm), and the phenomena, such as short-channel effect, would not appear. The simulation software was LTSPICE XVII, which is a SPICE software with graphical user interface. To construct model parameters, the measurement data of the 4H- SiC MOSFETs was used. The dimension of the transistors are tox = 20 nm and L/W = 10 m/50 m. The model parameters were extracted from MOSFET electrical characteristic and its fabrication parameters and physical constant. However, zero-bias threshold voltage and body-effect parameter were difficult to determine by the methods. Therefore, these parameters were assumed by comparing simulation results and measurement data. More details of the extraction of SPICE parameters are mentioned in Appendix A. In the SPICE2 model, the effect of temperature can be modeled by introducing temperature 38

41 Chapter 5. Modeling dependent parameters. However, this parameter does not give a good approximation for our measurement results. Hence, a separate SPICE model was constructed at each temperature condition in the range of ºC. 39

42 5.2. Modeling method Symbol TABLE II SPICE2 MOSFET MODEL PARAMETERS [37]. SPICE2G keyword LEVEL Parameter name Typical value for Si Units V TO VTO 1-3 Zero-bias threshold voltage 1 V KP KP 1-3 Transconductance parameter A/V 2 GAMMA 1-3 Body-effect parameter 0.35 V 1/2 2Φ p PHI 1-3 Surface inversion potential 0.65 V LAMBDA 1-3 Channel-length modulation 0.02 V -1 t ox TOX 1-3 Thin oxide thickness m N A NSUB 1-3 Substrate doping cm -3 N SS NSS 1-3 Surface state density cm -2 N FS NFS 2,3 Surface-fast state density cm -2 N eff NEFF 2 Total channel charge coefficient 5 X j XJ 2,3 Metallurgical junction depth m X jl LD 1-3 Lateral diffusion m T PG TPG 1-3 Type of gate material 1 μ 0 UO 1-3 Surface mobility 700 cm 2 /(V.s) U c UCRIT 2 Critical electric field for mobility V/cm U e UEXP 2 Exponential coefficient for mobility 0.1 U t UTRA 2 Transverse field coefficient 0.5 V max VMAX 2,3 Maximum drift velocity of carriers m/s X QC XQC 2,3 Coefficient of channel charge share 0.4 δ DELTA 2,3 Width effect on threshold voltage 1 κ KAPPA 3 Saturation field factor 1 η ETA 3 Static feedback on threshold voltage 1 θ THETA 3 Mobility modulation 0.05 V -1 a F AF 1-3 Flicker-noise exponent 1.2 k F KF 1-3 Flicker-noise coefficient I S IS 1-3 Bulk junction saturation current A J S JS 1-3 Bulk junction saturation current per square meter A/m 2 Φ j PB 1-3 Bulk junction potential 0.75 V C j CJ 1-3 Zero-bias bulk capacitance per square meter F/m 2 M j MJ 1-3 Bulk junction grading coefficient 0.5 C jsw CJSW 1-3 Zero-bias perimeter capacitance per meter F/m M jsw MJSW 1-3 Perimeter capacitance grading coefficient 0.33 F C FC 1-3 Forward-bias depletion capacitance coefficient 0.5 C GBO CGBO 1-3 Gate-bulk overlap capacitance per meter F/m C GDO CGDO 1-3 Gate-drain overlap capacitance per meter F/m C GSO CGSO 1-3 Gate-source overlap capacitance per meter F/m r D RD 1-3 Drain Ohmic resistance 10 Ω r S RS 1-3 Source Ohmic resistance 10 Ω R SH RSH 1-3 Source and drain sheet resistance 30 Ω 40

43 Chapter 5 Modeling 5.3. Parameters The constructed SPICE2 LEVEL2 model for SiC MOSFET is tabulated in Table III. Table III SPICE parameter for 4H-SiC NMOS in the range of 25ºC - 450ºC. SPICE2G Symbol 25ºC 50ºC 100ºC 150ºC 200ºC 250ºC 300ºC 350ºC 400ºC 450ºC Units keyword V TO VTO V KP KP 4.28E E E E E E E E E E-07 A/V 2 Γ GAMMA V 1/2 2Φ p PHI V λ LAMBDA 3.03E E E E E E E E E E-03 V -1 t ox TOX 2.00E E E E E E E E E E-08 m N A NSUB 6.00E E E E E E E E E E+17 cm -3 N FS NFS 1.42E E E E E E E E E E+13 cm -2 X jl LD m T PG TPG μ 0 UO 2.48E E E E E E E E E E+00 cm 2 /(V.s) U c UCRIT 1.92E E E E E E E E E E+07 V/cm U e UEXP U t UTRA I S IS 1.00E E E E E E E E E E-08 A C GDO CGDO 1.67E E E E E E E E E E-08 F/m C GSO CGSO 1.67E E E E E E E E E E-08 F/m R sh RSH Ω 41

44 Drain Current I DS 10-6 (A) Drain Current I DS (A) Normalized value Normalized value 5.4. Benchmark test results Figure 5.1 depicts the temperature dependence of each SPICE parameters. Saturation current IS, sheet resistance RSH, and transconductance parameter KP increase with temperature, on the other hand, the zero-bias threshold voltage VTO and surface inversion potential 2 p decrease with temperature VTO 0.6 λ Temperature (ºC) Fig. 5.1 SPICE parameters versus temperature. constant parameters with temperature is not plotted in this graph. Each parameter is normalized by maximum value. (a) SPICE parameters with temperature dependence, and (b) SPICE parameters with unclear temperature dependence Benchmark test results 2Φp IS Rsh KP (a) Temperature dependent parameters The simulated IDS - VGS characteristics compared with measurement is depicted in Fig There is good correlation with measurement above 3.5 V. However, the subthreshold current was not in good correlation with the measurement data NFS Uc Ue Temperature (ºC) (b) Other parameters 6.00E E E E-06 t ox = 20 nm L/W = 10 μm/50 μm T = ºC Simulation Measurement T 1.E E E E t ox = 20 nm L/W = 10 μm/50 μm T = ºC T E-06 1.E E E E Simulation Measurement 1.E Gate Voltage V GS (V) Gate Voltage V GS (V) Fig. 5.2 Simulated IDS-VGS characteristic and its comparison with measurement data, (a) linear scale, and (b) logarithmic scale. The simulated IDS-VDS property is depicted in Fig The simulation was in good correlation with the measurement data. 42

45 Drain current I DS (μa) Chapter 5 Modeling L/W = 10 μm/50 μm t ox = 20 nm T = 350 ºC V GS = 6 V V GS = 5 V V GS = 4 V V GS = 3 V Drain-source voltage V DS (V) Fig. 5.3 Simulated IDS-VDS characteristic comparison with measurement Discussion There was a large error at the subthreshold region in Fig The reason would be two points: (1) this model does not consider diffusion current, and (2) this model does not consider trap density. In this model, only drift current is considered, and the diffusion current is not considered. As reported in [38], the simulation at the subthreshold region can be improved by adding the diffusion current components. At the same time, there is no parameters for trap density in this model. However, the analysis of trap model is still difficult, and the SPICE model would be complicated. To improve the accuracy of simulation, further model parameters are needed. For MOSFET circuit simulation, plenty of models can be found and the accuracy of simulation can be improved, however, the number of model parameters are increased simultaneously Summary 4H-SiC MOSFET SPICE model was employed based on SPICE2 MOSFET LEVEL2 model. The parameters were extracted from L/W = 10 m/50 m and tox = 20 nm MOSFETs. To confirm its validity, the experimental result of MOSFET I-V static property was compared to the simulation, and the subthreshold region could not be replicated completely, however linear region and saturation region was good correlation with the measurement results in the range of ºC. 43

46 6. SiC circuits In this chapter, the further application of 4H-SiC integrated circuits is discussed. For analog circuits, operational amplifier is an important building block and its performance was simulated with the SiC MOSFET model. The inverters is also an important building block for digital circuits, and several types of inverter were simulated. Moreover, we discuss the merit of pseudo- CMOS further by calculating the device area and yield of pseudo-cmos integrated circuits Operational amplifier (Opamp) The operational amplifier is necessary in analog circuits application. The sensing system in Fig. 1.2 also needs amplifier to increase small electrical signal from the sensor. An operational amplifier (Opamp) is commonly used for this purpose. In this section, we simulate opamp circuit with new SiC SPICE model. As seen in 4H-SiC MOSFET I-V, the drain-current and threshold voltage change dramatically with temperature. Therefore, we need to take account temperature robustness into the circuit design. Figure 6.1 shows the circuit schematic of simulated circuit. This structure has one differential amplifier stage, current mirror, and source follower. R1 R2 R3 V DD = 5 V V OUT M1 M2 R1 50 Ω V IN R2, R3 300 kω M1, M2, M4 L/W =10 μm/500 μm M3 M4 M3 L/W =10 μm/50 μm Fig. 6.1 Operational amplifier with sheet resistance loads. The inset shows the value of each components. Figure 6.2 shows the simulated transfer results of the opamp. We can find that the characteristic depends on temperature. The maximum/minimum output voltage and the gain of amplifier increased with temperature. The gain, which is defined as maximum slope at the curve, is plotted as a function of temperature in Fig 6.3. The reasonable gain more than 1.0 times is gained from 200ºC. From the aspect of temperature robustness, this characteristic is not good at temperature varying environment. However, this structure would be applicable 44

47 Gain (times) Output voltage V out (V) Chapter 6 SiC circuits in high temperature and temperature stable conditions T = 25 ºC ºC T Input voltage V in (V) Fig. 6.2 Simulated output characteristic of operational amplifier Temperature (ºC) Fig. 6.3 Temperature dependency of voltage gain. We need still improvement for the SiC opamp, there are some options for the design. Firstly, we can use a PMOS loads in this circuits. The gain of PMOS loads operational amplifier does not depends on the drain current. Therefore, the performance variation with temperature can be avoided. In SiC technology, the consolidation of PMOS and NMOS is still on development. Secondly, we can also employ the NMOS load in the opamp. However, the gain of this circuit only depends on the size of transistor, and the gain is much lower than PMOS loads. We also simulated NMOS load opamp, and the circuit schematic and simulated transfer characteristic will be described in Appendix B. 45

48 6.2. Candidate of inverter 6.2. Candidate of inverter To evaluate the performance of the inverter, the temperature dependence was compared for other types of inverter. NMOS inverter, Pseudo-NMOS inverter, and CMOS inverter, which are shown in Fig. 3.10(b), (c) and (d), were simulated. The inverter voltage transfer characteristics (VTCs) were simulated and the supply current from supply voltage node (VDD) to ground (GND) were investigated. To simulate the operation of PMOS, transconductance parameter KP was assumed to be KPPMOS = 1/5 KPNMOS because PMOS has lower carrier mobility than NMOS. The simulation results for the NMOS-, pseudo-nmos, and CMOS- inverter are shown in Fig. 6.4, Fig. 6.5, and Fig. 6.6 respectively. Each VTC has a tendency, where the threshold voltage from 1 -state to 0 -state decreases with increasing temperature. This result indicates that the input voltage should take into account the variation of threshold voltage. The supply current flows at 0 - state and the current increased with temperature for NMOS and pseudo-nmos inverter, which causes large power dissipation to maintain a 0 -state. The VTC of NMOS inverter in Fig. 6.4(a) shows that the voltage at 1 -state decreased with input voltage, and the voltage was not constant with temperature. The configuration is needed more. As for pseudo-nmos inverter both 1 - and 0 - state had constant value and it is close to ideal inverter characteristic. However, the voltage at 0 -state is not completely zero. CMOS has almost ideal inverter characteristics, however the input voltage range was wide of 0 10 V because the high threshold voltage. 46

49 Output voltage V out (V) Supply current I t (μa) Output voltage V out (V) Supply current I t (μa) Output voltage V out (V) Supply current I t (μa) Chapter 6 SiC circuits T L 1 /W 1 = 10/10 μm L 2 /W 2 = 10/100 μm T = ºC L 1 /W 1 = 10/10 μm L 2 /W 2 = 10/100 μm T = ºC T T Input voltage V in (V) (a) Voltage transfer characteristic Input voltage V in (V) (b) Supply current characteristic Fig. 6.4 VTC and through current characteristic of NMOS inverter L 1 /W 1 = 10/10 μm L 2 /W 2 = 10/50 μm T = ºC T L 1 /W 1 = 10/10 μm L 2 /W 2 = 10/50 μm T = ºC T Input voltage V in (V) (a) Voltage transfer characteristic Input voltage V in (V) (b) Supply current characteristic Fig. 6.5 VTC and through current characteristic of pseudo-nmos inverter L 1 /W 1 = 10/50 μm L 2 /W 2 = 10/10 μm T = ºC T L 1 /W 1 = 10/50 μm L 2 /W 2 = 10/10 μm T = ºC T Input voltage V in (V) Input voltage V in (V) (a) Voltage transfer characteristic (b) Supply current characteristic Fig. 6.6 VTC and through current characteristic of CMOS inverter. 47

50 6.3. Operation analysis of pseudo-cmos 6.3. Operation analysis of pseudo-cmos In this section, the property variation of pseudo-cmos with temperature is discussed. Although the operation principle of pseudo CMOS has been discussed in several articles [31], [32], the high-temperature operation of pseudo-cmos is still not investigated. To understand the operation for each transistor in pseudo-cmos, the pseudo-cmos circuits were simulated with the SiC MOSFET SPICE model Simulation condition The simulated circuit is illustrated in Fig In this simulation, transistor M1 was substituted to a resistance of 10 M. The transistor size was set L/W = 50 m/50 m at each transistor. The simulation was conducted with the SiC MOSFET model in Table III. The reason transistor M1 was substituted with a resistance is that the SPICE simulator cannot simulate around zero gate-source voltage with the SiC MOSFET model. However, the current still flows in M1 in terms of leakage current through drain-bulk and source-bulk junctions, hence a high-resistance of 10 M would be suitable to approximate the operation. Moreover, it is important to note that M4 is operated at subthreshold region when Vin = 0 and the result would not be reliable at this region. VTC at first-stage inverter (V X ) and at second-stage inverter (V out ) are shown in Fig. 6.8 and Fig. 6.9 respectively. V SS V DD M1 M2 V in M3 V X M4 V out M1 10 MΩ M2, M3, M4 L/W = 50 μm/50 μm 1st stage 2nd stage Fig. 6.7 Schematic of simulated circuit. 48

51 Chapter 6 SiC circuits Fig. 6.8 Voltage transfer characteristic at the first stage of pseudo-cmos. Fig. 6.9 Voltage transfer characteristic at the second stage of pseudo-cmos Discussion of simulation results The output voltage of the first-stage VX decreased with input-voltage and its voltage swing increased with temperature. The gate-voltage of transistor M2 is equal to VX. Therefore, the transistor M2 cannot turn off when the voltage swing of the first-stage is low. The 0 -state of the pseudo-cmos is determined by the first stage, and its voltage-swing should be high enough to turn off M2. Figure 6.9 shows the correlation of voltage-swing of pseudo-cmos versus the ratio of conductance M1 and M3. Based on this figure, the conductance ratio K1/K3 needs to be at least 0.1, to achieve a voltage swing of 4.0V. 49

52 Voltage swing (V) 6.3. Operation analysis of pseudo-cmos K 3 /K 1 Fig Voltage swing of second-stage inverter (Vout) versus ratio of conductance M1 and M3. At the input voltage of V, the slope of the transfer characteristic in Fig. 6.9 increases with temperature, this is because of the increase of carrier mobility with temperature. The output voltage below Vin = 1.8 V is not constant, and this result does not follow Fig In this region, transistor M4 is operated at VGS = 0, therefore the simulation results would show incorrect results. Moreover, Fig. 4.8 shows that the voltage of 1 -state decreased dramatically at 400ºC and 450ºC. We could not find the reason of the output voltage decreasing at 400ºC and 450ºC from the simulation result. The reason would be that leakage current in M4 increased unexpectedly, so that the balance of VDS at transistor M2, M4 was changed. Based on the discussion, the operation principle of pseudo-cmos is described in Fig. 6.11; (1) In 1 -state, M3 has a leakage current and voltage drop appears at M3, and the VX decrease correspondingly. (2) the voltage swing of the first stage increases with temperature because of more current flows with temperature and the voltage drop of M3 increases. (3) In 1 -state, M4 also has a leakage current and voltage drop appears at M4, and Vout decreases correspondingly. (4) At T=T1, the voltage VX is too high to turn off M2, hence M2 is still ON. Both of M2 and M4 are ON and Vout is not pulled down to zero. (5) At T=T2, the voltage VX is enough to turn-off M2, hence M2 is OFF, M4 is ON and Vout is pulled down to zero. (6) The drain current at M4 increases with temperature, and the inverter gain increases. 50

53 Chapter 6 SiC circuits V SS V X (1) V DD V out (3) T = T 1 T = T 3 (4) (2) T = T 2 (6) (5) T = T 1 T = T 2 (a) Output voltage of first-stage Fig Operation principle of pseudo-cmos Design of pseudo-cmos V in (b) Output voltage of second-stage Based on Fig. 6.10, High-conductance is needed in transistor M3 to turn-off M2, therefore, the mobility of transistor should be increased. Long gate-width would be also effective to increase high-conductance at M3, however high-gate width would induce high-leakage current and voltage drop (1) in Fig as well. Hence, the gate-width should be optimized not to decrease the voltage at 1 -stage at first-stage inverter. M4 is also required in high-conductance and low leakage current. As described in section 3.3, the pseudo-cmos was designed in L/W = 5 m /1500 m and 5 m /5000 m MOSFETs; however, the size of transistor is not needed in such a large transistor based on the simulation, and further scaling is available. V in 6.4. Yield calculation of 4H-SiC integrated circuits In this section, the development of SiC integrated circuits is discussed. CPU and memory are necessary for harsh-environment electronics as shown in Fig Therefore, it is important to know the integration level in terms of device area and yield. This discussion would be a prerequisite to design and fabricate more complicated SiC circuits. In this calculation, we employ integrated circuit either with CMOS or pseudo- CMOS. The area of the inverter, which is elemental building block for logic circuits is Pseudo- Apseudo CMOS 3 ANMOS 0.3ANMOS 3.3ANMOS, (6.1) CMOS: CMOS: ACMOS ANMOS APMOS ANMOS 5A NMOS 6ANMOS, (6.2) where ANMOS is the area of one NMOS and APMOS the area of one PMOS. The area of PMOS should be designed 5 times larger than NMOS because of 5 times difference in mobility between PMOS and NMOS. Whereas there is one smaller NMOS in pseudo-cmos, therefore 0.3 times smaller area of NMOS is considered. Figure 6.11 illustrates the comparison of the area between CMOS and pseudo-cmos inverter. The area of CMOS was dominated by PMOS, and the area of pseudo-cmos arises from four NMOSs. In the next subsections, the 51

54 6.4. Yield calculation of 4H-SiC integrated circuits calculation methods of yield and device area and the calculation results are explained. PMOS 1 NMOS 4 (a) CMOS NMOS 1 Fig Comparison of the area of CMOS and pseudo-cmos Calculation method (b) pseudo-cmos This calculation assumed that a CPU is composed of three parts: registers, arithmetic logic unit (ALU), and control unit. The functions of them are storing temporary data, calculation, and the query of input/output respectively. The architecture of the CPU is illustrated in Fig and the components of CPU and memory is tabulated in Table IV. Register ALU DB Memory Control Unit DB: Data bus ALU : Arithmetic logic unit Fig Architecture of SiC CPU and memory. 52

55 Chapter 6 SiC circuits Table IV Description of components for SiC CPU and memory. Component Description Register 10 8-bit register ALU 8-bit full-adder Control Unit 8 to 1 multiplexer Memory DRAM matrix shift-register D C C(k-1) A(k) 2-input NAND 8 + NOT 2 Q Q (a) D-flipflop 2-input NAND 9 S(k) d0 d1 d2 d3 d4 d5 a2 a1 a0 4-input NAND input NAND + NOT 3 X d6 B(k) C(k) d7 (b) 1-bit full adder (c) 8 to 1 multiplexer Fig Circuit diagram of NAND Logic, (a) D-flipflop, (b) 1-bit full adder, (c) 8 to 1 multiplexer. Word line Bit line NMOS 1 + Capacitor 1 M1 C1 Fig Circuit diagram of a DRAM cell. The circuit diagram of components is illustrated in Fig These components consist of NAND logic. The 1-bit register is employed with D-latch flip flop (D-FF) which consists of 4 of 2-input NAND. 1-bit full adder consists of 9 of 2-input NAND. 8 to 1 multiplexer consists of 8 of 4-input NAND, 1 of 8- input NAND, and 1 inverter. 1-bit DRAM cell consists of 1 transistor and 1 capacitor. there is a shift register to read data from a cell in DRAM matrix as well. In this calculation, 10 8-bit register, 8-bit ALU, and 8 to 1 bit multiplexer were considered for CPU, and DRAM memory with cells and 2 10 shift 53

56 6.4. Yield calculation of 4H-SiC integrated circuits register was considered for the memory. The size of NMOS was assumed in L/W = 50 m/100 m, and PMOS was assumed in L/W = 50 m/500 m, because this simulation assumed that PMOS and NMOS is 5:1. Based on this condition, the total-area of CPU and memory cell were estimated. The area of components was calculated from counting the number of NAND gate and calculating the area of NAND gate. The area of n-input NAND gate is calculated from ANAND ninv Ainv, (6.3) where ninv is number of CMOS/pseudo-CMOS inverter, and Ainv the area of CMOS/pseudo-CMOS inverter. The components are composed of NAND gate, and therefore the area of the component is Acomponent nnand ANAND, (6.4) where nnand is the number of NAND gate at the component. The area of CPU and memory is the sum of the area of components, A Acomponent () i. (6.5) i Next, the yield of CPU and memory was considered. To calculate yield, a device-killing defect density ndefect is defined. The yield of device Y is calculated using this equation: Y n A. (6.6) 1 defect Using the equations, the device area and the yield of CPU and memory were calculated Calculation result The comparison of device area is tabulated in Table V and the calculated yield at defects density of 1.0 cm -2 is tabulated in Table VI. The comparison of device area between CMOS and pseudo-cmos is illustrated in Fig The area of CPU with pseudo-cmos is 45% smaller than CMOS, whereas the area of memory with pseudo-cmos is 43% smaller than CMOS. The yield of pseudo- CMOS achieved 90% at defects density of 1.0 cm -2. In addition, Figure 6.17 illustrates the yield as a function of defects density. The difference of yield between CMOS and pseudo-cmos increases with the defects density. Hence, pseudo-cmos circuits is more reliable than CMOS circuits. Based on these results, Integrated circuits with pseudo-cmos is competitive circuit design in terms of device area and yield. Not only these aspects, the processing technology of CMOS has more complexity than pseudo-cmos. Therefore, pseudo-cmos integrated circuits is an effective way to construct the sensing system in Fig

57 Area of device (μm 2 ) Yield (%) Chapter 6 SiC circuits Table V Device area of SiC logic components. Device Area of CMOS Area of pseudo-cmos (μm 2 ) (μm 2 ) D-FF (Register) bit-adder (ALU) multiplexer (Decoder) Memory CPU Table VI Yield of CPU and memory (defects density = 1.0 cm -2 ). CMOS Pseudo-CMOS Yield of CPU (%) Yield of Memory (%) CMOS Pseudo- CMOS CMOS Pseudo- CMOS Defect density = 1 (cm -2 ) Pseudo- CMOS Pseudo- CMOS CMOS CMOS Memory CPU 60 Memory CPU (a) Area of device (b) Yield Fig Comparison of device area and yield between CMOS and pseudo- CMOS (defects density = 1.0 cm -2 ). 55

58 Area of CPU (μm ) Area of circuit (μm 2 ) Yields (%) 6.4. Yield calculation of 4H-SiC integrated circuits Pseudo-CMOS CPU Pseudo-CMOS Memory CMOS CPU CMOS Memory Defects density (cm -2 ) Fig The yield of device versus device-killing defects density Scaling of pseudo-cmos integrated circuits Scaling of device area is derived in Fig At the starting point, the device area is around 10 8 m 2, and the device size is diminished to 10 5 m 2 beyond 10 m-scaling. Not only pseudo-cmos, CMOS integrated circuits would also be developed and there is a possibility to scale more by means of breakthrough of mobility enhancements. 1.E E E E SiC pseudo-cmos 8-bit CPU 1.E Gate width Width (μm) Fig Prediction of the integration of 4H-SiC MOSFETs. 56

59 Chapter 6 SiC circuits 6.5. Summary We applied the SiC SPICE model into the circuit simulation. A 4H-SiC operational amplifier was simulated in the range of 25ºC to 450ºC. NMOS inverter, pseudo-nmos inverter and CMOS inverter were also simulated from 25ºC to 450ºC. It was shown that the gain of opamp increases with temperature, and PMOS-load is needed to achieve temperature-stable gain. Moreover, the operation principle of pseudo-cmos inverter was shown based on the simulation results. We conducted device area and yield calculation to estimate future SiC integrated circuits. The device area of pseudo-cmos circuits was compared to CMOS circuits, and the device area of CPU and memory decreased 45% and 43% respectively. The yield was also compared, and the pseudo-cmos CPU and memory has improved yield. 57

60 7. Conclusions and Future work In this thesis, 4H-SiC MOS devices in high-temperature has been characterized to construct model parameters. The operation of Pseudo-CMOS at temperatures higher than 300ºC has been demonstrated, and the temperature dependency of contact resistivity and sheet resistance has been discovered as well. Based on the results, circuit simulation models for 4H-SiC MOSFETs were constructed and it enables us to design 4H-SiC circuit in the range of ºC. The temperature dependency of the MOSFET is mainly observed as the decrease of zero-bias threshold voltage and the increase of transconductance. Based on the circuit model, the operation principle of pseudo-cmos has been analyzed, and this analysis gives the needs: (1) increase of carrier mobility and (2) decrease of off-state leakage currents. Based on the estimation of device area and yield of SiC integrated circuits, Pseudo-CMOS circuits had about 45% smaller device area than CMOS circuits, and higher yield. For the future work, the device layout and fabrication of operational amplifier and components for inverter will be conducted. Pseudo-CMOS can be scaled more based on our discussion, and an optimization of the size of pseudo- CMOS is required. Furthermore, SiC processing technology should be improved to enlarge the application of SiC circuits. For example, a device structure to minimize gate overlap capacitance is desired for high-frequency operation. Carrier mobility of the MOSFETs should be increased to gain higher gain of inverter and operational amplifier. To gain more accurate simulation results, more advanced circuit model such as SPICE2 LEVEL3, or BSIM1 are needed. The fabrication of test element group (TEG) would be an effective way to extract model parameters. 58

61 Reference [1] H. Nagatsuma, 4H-SiC MOSFETs による極限環境応用デバイスの研究, Hiroshima University, [2] K. C. Reinhardt and M. A. Marciniak, Wide-bandgap power electronics for the More Electric Aircraft, in IECEC 96. Proceedings of the 31st Intersociety Energy Conversion Engineering Conference, 1996, vol. 1, pp [3] David R. Williams, Venus Fact Sheet, [Online]. Available: [Accessed: 08-Nov-2016]. [4] S. Kawatsuma, Radiation Tolerance of Components On The Shelf, in International Workshop on Radiation Resistant Sensors and Related Technologies for Nuclear Power Plant Decommissioning 2016 (R2SRT2016), 2016, pp [5] P. Neudeck, R. Okojie, and L. Chen, High-temperature electronics-a role for wide bandgap semiconductors?, Proceedings of the IEEE, vol. 90, no. 6, pp , [6] K. Tanaka, 高品質 SiC MIS デバイスの製造プロセスに関する研究, Tohoku University, Sendai, [7] KTH Royal Institute of Technology, WOV Working on Venus, [Online]. Available: [Accessed: 08-Dec- 2016]. [8] S. I. Kuroki, H. Nagatsuma, M. de Silva, S. Ishikawa, T. Maeda, H. Sezaki, T. Kikkawa, T. Makino, T. Ohshima, M. Östling, and C. M. Zetterling, Characterization of 4H-SiC nmosfets in Harsh Environments, High- Temperature and High Gamma-Ray Radiation, Materials Science Forum, vol. 858, pp , [9] S. Kuroki, H. Nagatsuma, T. Kurose, S. Ishikawa, and T. Maeda, 4H-SiC Pseudo-CMOS Logic Inverters for Harsh Environment Electronics, in 11th European Conference on Silicon Carbide and Related Materials (ECSCRM2016), 2016, vol. WeP, no. 27, pp [10] H. Nagatsuma, S. I. Kuroki, M. de Silva, S. Ishikawa, T. Maeda, H. Sezaki, T. Kikkawa, M. Östling, and C. M. Zetterling, 4H-SiC nmosfets with As-Doped S/D and NbNi Silicide Ohmic Contacts, Materials Science Forum, vol. 858, pp , [11] M. De Silva, S. Ishikawa, T. Miyazaki, T. Kikkawa, and S. I. Kuroki, Formation of amorphous alloys on 4H-SiC with NbNi film using pulsedlaser annealing, Applied Physics Letters, vol. 109, no. 1, [12] T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications. John Wiley & Sons Singapore Pte Ltd., [13] T. Ayalew, SiC Semiconductor Devices Technology, Modeling, and Simulation, TU Wien,

62 Reference [14] C.-M. Zetterling, Integrated circuits in silicon carbide for hightemperature applications, MRS Bulletin, vol. 40, no. 5, pp , [15] C.-M. Zetterling, Process Technology for Silicon Carbide Devices, EMIS proce. London: The Institution of Electrical Engineers, [16] T. Kimoto, Material science and device physics in SiC technology for high-voltage power devices, Japanese Journal of Applied Physics, vol. 54, no. 4, p , [17] L. Lanni, Silicon Carbide Bipolar Integrated Circuits for High Temperature Applications, KTH, Royal Institute of Technology, [18] Y. Tian, L. Lanni, A. Rusu, and C. M. Zetterling, A 500 C Monolithic SiC BJT Latched Comparator, Materials Science Forum, vol. 858, pp , May [19] S. Singh and J. A. Cooper, Bipolar integrated circuits in 4H-SiC, IEEE Transactions on Electron Devices, vol. 58, no. 4, pp , [20] M. Alexandru, V. Banu, X. Jorda, J. Montserrat, M. Vellvehi, D. Tournier, J. Millan, and P. Godignon, SiC Integrated Circuit Control Electronics for High-Temperature Operation, IEEE Transactions on Industrial Electronics, vol. 62, no. 5, pp , May [21] M. Alexandru, V. Banu, M. Vellvehi, P. Godignon, and J. Millan, Design of Digital Electronics for High Temperature Using Basic Logic Gates Made of 4H-SiC MESFETs, Materials Science Forum, vol. 711, pp , [22] P. G. Neudeck, S. L. Garverick, D. J. Spry, L. Y. Chen, G. M. Beheim, M. J. Krasowski, and M. Mehregany, Extreme temperature 6H-SiC JFET integrated circuit technology, Physica Status Solidi (A) Applications and Materials Science, vol. 206, no. 10, pp , [23] S. Kuroki, H. Nagatsuma, T. Kurose, S. Ishikawa, and T. Maeda, 4H-SiC Pseudo-CMOS Logic Inverters for Harsh Environment Electronics, in the 11th European Conference on Silicon Carbide and Related Materials (ECSCRM), [24] D. T. Clark, E. P. Ramsay, A. E. Murphy, D. a. Smith, R. F. Thompson, R. a. R. Young, J. D. Cormack, C. Zhu, S. Finney, and J. Fletcher, High Temperature Silicon Carbide CMOS Integrated Circuits, Materials Science Forum, vol , pp , [25] E. Ramsay, J. Breeze, D. Clark, A. Murphy, D. Smith, R. Thompson, S. Wright, R. Young, and A. Horsfall, High Temperature CMOS Circuits on Silicon Carbide, Materials Science Forum, vol , pp , Jun [26] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices 2nd Edition. Cambridge University Press, [27] D. K. Schroder, Contact resistance and schottky barriers, Semiconductor Material and Device Characterization, pp , [28] H. H. Berger, Models for contacts to planar devices, Solid State Electronics, vol. 15, no. 2, pp , [29] K. Fukuda, T. Sekitani, T. Yokota, K. Kuribara, T. C. Huang, T. Sakurai, U. Zschieschang, H. Klauk, M. Ikeda, H. Kuwabara, T. Yamamoto, K. 60

63 Reference Takimiya, K. T. Cheng, and T. Someya, Organic pseudo-cmos circuits for low-voltage large-gain high-speed operation, IEEE Electron Device Letters, vol. 32, no. 10, pp , [30] T. C. Huang, K. Fukuda, C. M. Lo, Y. H. Yeh, T. Sekitani, T. Someya, and K. T. Cheng, Pseudo-CMOS: A design style for low-cost and robust flexible electronics, IEEE Transactions on Electron Devices, vol. 58, no. 1, pp , [31] E. Cantatore, T. C. T. Geims, a F. a Gruijthuijsen, G. H. Gelinck, S. Drews, and D. M. De Leeuw, A MHz RFID System based on Organic Transponders, Proc ISSCC, vol. 15.2, no. 1, pp , [32] E. Cantatore and E. J. Meijer, Transistor operation and circuit performance in organic electronics, ESSCIRC th European Solid-State Circuits Conference (IEEE Cat. No.03EX705), pp , [33] L. W. Nagel and D. O. Pederson, SPICE (Simulation Program with Integrated Circuit Emphasis), [34] L. W. Nagel, SPICE2: A Computer Program to Simulate Semiconductor Circuits, EECS Department, University of California, Berkeley, [35] A. Akturk, N. Goldsman, A. Ahyi, S. Dhar, B. Cusack, and M. Park, SPICE Modeling of Advanced Silicon Carbide High Temperature Integrated Circuits, Materials Science Forum, vol. 858, pp , [36] P. G. Neudeck, D. J. Spry, and L. Y. Chen, Experimental and Theoretical Study of 4H-SiC JFET Threshold Voltage Body Bias Effect from 25 C to 500 C, Materials Science Forum, vol. 858, no. 2, pp , May [37] G. Massobrio and P. Antognetti, Semiconductor Device Modeling With Spice. New York: Mcgraw-Hill, [38] P. Antognetti, D. D. Caviglia, and E. Profumo, CAD Model for Threshold and Subthreshold Conduction in MOSFET s, IEEE Journal of Solid-State Circuits, vol. 17, no. 3, pp , [39] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill,

64 Appendix A Appendix A SPICE parameter extraction In this appendix, the method of extracting SPICE MOSFET LEVEL2 parameters is explained in detail. The way of extraction can be referred to the literature as well [37]. However, some of parameters are determined with this thesis s own method. A.1 Delimitation of modeling The constructed model in Table III is Level2 model, and therefore, the shortchannel effect cannot be simulated. The gate length L is smaller than 5 m, the additional models (for example, Level3 models) should be constructed. In this simulation model, linear region and saturation region can be simulated; however, the simulation result of subthreshold region would be unreliable. For the SPICE simulation, the gate-voltage should be set around and above threshold voltage. The dimension of transistor should not be less than 5 m. The oxide thickness should not be changed from 20 nm. A.2 Parameter extraction from MOSFET I-V characteristic Oxide capacitance C ox Oxide capacitance is calculated from s COX (F/cm 2 ), (A.1) t OX where s is the permittivity of the oxide, tox the thickness of gate oxide. Surface inversion potential 2 p This parameter is related to the threshold voltage, and the value is theoretically determined: 2 kt N A p 2 ln( ) q n (V), (A.2) i where k is Boltzmann constant, T temperature, q electronic charge, NA substrate doping, ni intrinsic density, depends on temperature. ni can be found in the literature (for example, the values are found in [12]) as the figure of intrinsic density versus temperature. Fast state density N FS Fast state density is correlated to the subthreshold region and this is calculated from 62

65 Drain Current I DS (A) Appendix A VGS q COX NFS 1 (cm log10 IDS kt q -2 ), (A.3) where VGS/ log10ids is extracted from log-scaled IDS-VGS characteristic. 1.00E E t ox = 20 nm L/W = 10 μm/50 μm V DS = 0.5 V T = 450 ºC 1.00E Is log I S DS V GS E Gate Voltage V GS (V) Fig. A.1 Extraction of Subthreshold slope for fast state density. Transconductance parameter KP and zero-bias threshold voltage V TO KP and the threshold voltage VTH is gained by the IDS-VGS property. To gain them, a tangent line should be drawn as described in Fig. A.2, KP can be calculated from the slope of line, and the VTH is gained from the intercept to x- axis. The zero-bias threshold voltage is gained from subtracting offset value from VTH. The offset value is defined as 0.55 V in our model. Based on [37], the threshold voltage is equal to zero-bias threshold voltage; however, there was difference between simulation and measurement. Therefore, the offset value was introduced. It is thought that the drain bias in our VGS-IDS measurement was relatively high (0.5 V), therefore the threshold voltage was estimated higher. Based on the discussion, KP and VTO are determined from slope KP ( W / L) V (A/V2), (A.4) DS VTO VTH Vshift (V), (A.5) where slope is the slope of curve at the IDS-VGS characteristic, W/L size ratio of transistor, Vshift the offset value, 0.55 V. The example of extracting VTO and KP is illustrated in Fig. A.2. 63

66 log(kp /KP) Drain Current I DS 10-6 (A) Appendix A 6.00E E E E-06 t ox = 20 nm L/W = 10 μm/50 μm T = 450 ºC I DS = KP(W/L)(V GS -V TH )V DS E E-06 slope = KP(W/L)V DS V TH 0.00E Gate Voltage V GS (V) Fig. A.2 Extraction of transconductance parameter KP and zero-bias threshold voltage VTO from IDS-VGS property. V ON KP variation term U e and U c These parameters are used to compensate the variation of transconductance KP with VGS. The variation of KP is approximated with this empirical equation, KP where Uc and Ue are determined with the measurement, Ut is assumed as 0.5. Plotting log(kp /KP) log(vgs VTH UTVDS) and a linear regression. These variation terms are calculated from (A.7) U 0.25 s c ox KP ox VGS VTH UtVDS U e Ut a, OX / 10 ba c (V/m). (A.8) tox s U e, (A.6) t ox = 20 nm W/L = 50 μm/10 μm V DS = 0.5 V T = 450 ºC a = e-2 b = 1.80 e y x log(v GS -V TH -U T V DS ) Fig. A.3 Extraction of exponential coefficient of mobility Ue and critical electric field of mobility Uc from log(kp /KP)-log(VGS-VTH-UTVDS) property. 64

67 Drain current I DS (A) Appendix A Channel-length modulation The drain current at the saturation region at IDS-VDS characteristic is theoretically constant. However, the drain current at the saturation region depends on drain-source voltage in actual fact. This phenomenon is because of the modulation of channel-length. This parameter is used to simulate the channel length modulation: G D, sat (V -1 ), (A.9) I where ID,sat is saturation current and GD,sat is conductance. These parameters are defined in Fig. A.4. ID,sat is determined from the point of the curve at saturation, and G D,sat is determined from the slope of saturation region. 5.0 D, sat 4.0 G D,sat I D,sat t ox = 20 nm L/W = 10 μm/50 μm V GS = 5 V T = 350 ºC Drain-source voltage V DS (V) Fig. A.4 Extraction of channel-length modulation from IDS-VDS property. Type of gate material T PG Type of gate material TPG is 0, because the gate is made of aluminum. Bulk junction current I s Bulk junction current IS is extracted from IDS-VGS characteristic, and IS is defined as the drain current at VGS = 0. Gate-Drain/Source overlap capacitance per meter C GDO, C GSO This value is directly determined from high-frequency C-V measurement between gate and source/drain of MOSFET. In the measurement, the gate was biased and the source and drain were grounded. The MOSFET is 4H-SiC L/W = 5/1500 m, tox = 20 nm. The dielectric is silicon dioxide. The measurement result is depicted in Fig. A.5. The capacitance would be composed of the overlap capacitance between gate and source/drain, and the edge of channel. The 65

68 Appendix A capacitance from the channel depends on the gate voltage, and therefore the capacitance increased with gate voltage. From the measurement, the total overlap capacitance was estimated to be (F), the value was normalized by the gate length, and divided by half to gain gate-source overlap capacitance and gate-drain capacitance respectively. Hence, CGSO = CGDO = (F/m)., and the overlap capacitance was assumed constant with temperature. Capacitance (F) C-V at Gate-Drain/Source 4H-SiC MOSFET L/W = 5 μm/1500 μm t ox = 20 nm T = 25 ºC Gate voltage (V) Fig. A.5 High-frequency C-V characteristic at gate-drain/source overlap capacitance. Body effect The body effect is calculated theoretically: 2 sqna, (A.10) C ' where s indicates the permittivity of the semiconductor, q is the elementary charge, N A is the doping concentration of substrate. Although the body effect is calculated theoretically, can be directly measured by means of back-side bias of the MOSFET. However, the back-side contact is not formed in our device and the value could not be measured. Moreover, the proper body effect could not be gained with (A.10). It is probably the case that the doping profile is not homogenous, which caused errors in the simulation. Therefore, was arbitrarily determined to fit the characteristic. A.3 Implementation of SiC MOSFET SPICE model To execute the SPICE model, the following.model statement should be written in SPICE code. Each MOSFET should be assigned the model name, 4H-SiC_XXdegC, where XX means the magnitude of temperature of the simulation. The device simulation is available for the parabolic region and saturation region. The sub-threshold region is however, not good in simulation. The parasitic capacitance such as gate to source, gate to drain capacitance was not included in the model. Thus, transient and AC simulation would OX 66

69 Appendix A overestimate the maximum frequency. Table VII SPICE.MODEL statement for 4H-SiC MOSFET. 25ºC.MODEL 4HSiC_25degC NMOS (LEVEL=2 VTO=2.69 KP= GAMMA=4.5 PHI= LAMBDA= TOX= NSUB= NFS= LD=0 TPG=0 U0 = UCRIT= UEXP= UTRA=0.5 IS= CGDO=1.667e-8 CGSO=1.667e-8 RSH = ) 50ºC.MODEL 4HSiC_50degC NMOS (LEVEL=2 VTO=2.72 KP= GAMMA=4.5 PHI= LAMBDA= TOX= NSUB= NFS= LD=0 TPG=0 U0 =0.048 UCRIT= UEXP= UTRA=0.5 IS= CGDO=1.667e-8 CGSO=1.667e-8 RSH = ) 100ºC.MODEL 4HSiC_100degC NMOS (LEVEL=2 VTO=2.55 KP= GAMMA=4.5 PHI= LAMBDA= TOX= NSUB= NFS= LD=0 TPG=0 U0 = UCRIT= UEXP= UTRA=0.5 IS= CGDO=1.667e-8 CGSO=1.667e-8 RSH =3.8775) 150ºC.MODEL 4HSiC_150degC NMOS (LEVEL=2 VTO=2.4 KP= GAMMA=4.5 PHI= LAMBDA= TOX= NSUB= NFS= LD=0 TPG=0 U0 = UCRIT= UEXP= UTRA=0.5 IS= CGDO=1.667e-8 CGSO=1.667e-8 RSH = ) 200ºC.MODEL 4HSiC_200degC NMOS (LEVEL=2 VTO=2.49 KP= GAMMA=4.5 PHI= LAMBDA= TOX= NSUB= NFS= LD=0 TPG=0 U0 = UCRIT= UEXP= UTRA=0.5 IS= CGDO=1.667e-8 CGSO=1.667e-8 RSH = ) 250ºC.MODEL 4HSiC_250degC NMOS (LEVEL=2 VTO=2.33 KP= GAMMA=4.5 PHI= LAMBDA= TOX= NSUB= NFS= LD=0 TPG=0 U0 = UCRIT= UEXP= UTRA=0.5 IS= CGDO=1.667e-8 CGSO=1.667e-8 RSH = ) 300ºC.MODEL 4HSiC_300degC NMOS (LEVEL=2 VTO=2.21 KP= GAMMA=4.5 PHI= LAMBDA= TOX= NSUB= NFS= LD=0 TPG=0 U0 = UCRIT= UEXP= UTRA=0.5 IS= CGDO=1.667e-8 CGSO=1.667e-8 RSH = ) 350ºC.MODEL 4HSiC_350degC NMOS (LEVEL=2 VTO=1.84 KP= GAMMA=4.5 PHI= LAMBDA= TOX= NSUB= NFS= LD=0 TPG=0 U0 = UCRIT= UEXP= UTRA=0.5 IS= CGDO=1.667e-8 CGSO=1.667e-8 RSH = ) 400ºC.MODEL 4HSiC_400degC NMOS (LEVEL=2 VTO=1.65 KP= GAMMA=4.5 PHI= LAMBDA= TOX= NSUB= NFS= LD=0 TPG=0 U0 = UCRIT= UEXP= UTRA=0.5 IS= CGDO=1.667e-8 CGSO=1.667e-8 RSH = ) 450ºC.MODEL 4HSiC_450degC NMOS (LEVEL=2 VTO=1.66 KP= GAMMA=4.5 PHI= LAMBDA= TOX= NSUB= NFS= LD=0 TPG=0 U0 = UCRIT= UEXP= UTRA=0.5 IS= CGDO=1.667e-8 CGSO=1.667e-8 RSH = ) 67

70 Appendix B Appendix B SiC operational amplifier with diode-connected loads In this section, the simulation results of NMOS load (diode-connected) opamp is described. For real application, SiC opamp needs temperature robustness at temperature varying environments. The schematic of the operational amplifier illustrated in Fig. B.1. This structure is composed of 2 stages of differential amplifier. The gain of NMOS load amplifier depends on the size of transistor only. Therefore, the gain of the circuit is not be affected by the drain current [39]. Therefore, the gain is not affected by temperature variation. The operational amplifier was simulated using LTSPICE XVII. The parameters were used from Table III. The diodeconnected loads (M1, M2, M3, and M4) have 1 V-smaller threshold voltage than other NMOSs to widen the input voltage range of the opamp. M1, M2, M3, M4 L/W = 0/20 μm, 1V-smaller threshold voltage M5, M6, M7, M8 L/W = 10/200 μm M9, M10, M11 L/W = 10/50 μm V DD = 7 V 10 kω M1 M2 M3 M4 V IN M5 M6 M7 M8 V OUT M9 M10 M11 Fig. B.1 Circuit diagram of operational amplifier. The resistance value and transistor size were used in SPICE simulation. To widen the input range, the active loads, M1 M4 have 1 V-smaller threshold voltage. The simulation result is shown in Fig. B.2. The range of input voltage is shifted with temperature. It is because of the threshold voltage variation. The gain of the operational amplifier was of 4 and constant with temperature. The gain of this opamp is low and it cannot be used in application. 68

71 Output voltage V out (V) Appendix B Opamp ºC Gain = Input voltage V in (V) Fig. B.2 Simulated output characteristic of operational amplifier. T 69

72 TRITA -ICT-EX-2017:10