Institutionen för systemteknik

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1 Institutionen för systemteknik Department of Electrical Engineering Examensarbete REALIZATION OF CASCADE OF RESONATORS WITH DISTRBUTED FEED-BACK SIGMA-DELTA Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping av Jawad Saleem Abdul Mateen Malik LiTH-ISY-EX--09/4314--SE Linköping 2009 Department of Electrical Engineering Linköpings universitet SE Linköping, Sweden Linköpings tekniska högskola Linköpings universitet Linköping

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3 REALIZATION OF CASCADE OF RESONATORS WITH DISTRBUTED FEED-BACK SIGMA-DELTA Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping av Jawad Saleem Abdul Mateen Malik LiTH-ISY-EX--09/4314--SE Handledare: Examinator: Supervisor Per Löwenborg, Linköpings universitet Examiner Per Löwenborg, Linköpings universitet Linköping, 14 August, 2009

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5 Avdelning, Institution Division, Department Department of Electrical Engineering Department of Electrical Engineering Linköpings universitet SE Linköping, Sweden Datum Date Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport ISBN ISRN LiTH-ISY-EX--09/4314--SE Serietitel och serienummer Title of series, numbering ISSN URL för elektronisk version Titel Title REALIZATION OF CASCADE OF RESONATORS WITH DISTRBUTED FEED-BACK SIGMA-DELTA Författare Author Jawad SaleemAbdul Mateen Malik Sammanfattning Abstract The Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost. The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry. Nyckelord Keywords sigma-delta modulator, operational transconductance amplfier, analog to digital converter, digital to analog converter, signal flow graph

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7 Abstract The Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost. The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry. v

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9 Acknowledgments In The Name of Allah The Most Beneficent the Most Merciful. We are very much thankful to our supervisor Dr. Per Löwenborg for his kind support, help and guidance. We are very thankful to our parents, grand parents, teachers and families who encouraged us and prayed for our success. We are thankful to our friend Khurram Shahzad, Abdul Majid, Abdul Whaeed for their support, time and help in all respects. We are thankful to Peter Johansson for his help regarding computers and software availibility. We are also thankful to Fahad Qazi and Farooq-ul-Amin for their comments on our thesis. We are also thankful to HEC Pakistan for their support. vii

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11 Contents 1 Introduction Why sigma-delta Goals of the project Specifications Design challenges Work flow Limitations Sigma-Delta Modulator Basic concept of SDM Oversampling Noise shaping Limitations of SDM CRFB with feed forward and feed back connections Methodology Matlab realization Coefficient calculation for third-order SDM Matlab model of the third-order CRFB SDM Maximum stable input range Clocking for SC SDM Clock generation module Switched-capacitor realization of SDM Realization from SFG to SC network OTA modeling for SDM Small signal model Analog to digital converter Introduction Resolution of ADC Quantization Architecture ix

12 x Contents 7.5 Behavioral level design Circuit realization Comparator Inverter and SR-latch Simulation results of ADC Digital to analog converter Introduction Behavioral level design Circuit realization Simulation results Results Results SC realization of the SDM structure OTA modeling Simulation results Matlab model results Cadence model results Bibliography 51

13 List of Figures 1.1 Principle amplitude spectrum of a multicarrier WCDMA signal Heterodyne receiver architecture First-order sigma-delta modulator with 3-bit quantizer FFT analysis showing signal and quantization noise for a Nyquist rate ADC FFT analysis illustrating oversampling FFT analysis showing shaped noise Third-order SDM with interconnections Third-order SDM with placement of delays Magnitude response of the third-order SDM General structure of a three bit quantizer sigma-delta modulator Pole-zero plot for L0 and L Integrator model for Matlab Precedence graph for third-order SDM Output spectrum of third-order SDM Filtered signal amplitude spectrum SNDR versus input signal amplitudes MSIR (minimum of the maximum amplitudes) Clock timing diagram Non-overlapping clock generator Clock generator schematics results Third order SDM Third order SDM with full or half delay at the integrator input A general integrator model Inverting and non inverting connection Integrator with two inverting inputs Integrator having one inverting and one non inverting input Fully differential SC CRFB network SC integrator with several inputs Return ratio model of the SC integrator Two pole small signal model SFG with error sources used to simulate SNDR degradation due to incomplete settling SNDR vs Error bound Three-bit flash ADC with decoder Comparator schematics The SR-latch Test bench for the ADC Simulation results of ADC schematic design

14 2 Contents 8.1 Architecture of DAC element SC DAC structure for the SDM Test bench setup to check the functionality of the DAC Simulations results from the schematic of DAC Output spectrum of the third-order modulator Test bench for the third-order CRFB SDM Simulation results from cadence model

15 Chapter 1 Introduction In the introductory chapter, we discuss why there is a need of Sigma Delta A/D converter in newer trends and what are the main goals of our project, as we worked on Sigma Delta Modulator so the Objectives, Limitations in our thesis and the design flow through which we proceed will be described. 1.1 Why sigma-delta The signal processing tasks are mostly performed in digital domain because of the robustness, increasing speed and the inexpensive implementation of the digital circuits. As most of the signals are analog there be a need for the data converters, a very important block in the communication system and the interface between the analog world and digital domain. Sigma Delta Analog to Digital conversion is commonly used in many communication applications because of its high-speed and accuracy. As opposed to Nyquist rate data converter, sigma delta data converter employ oversampling and noise shaping. These concepts are described in detail in upcomming chapters. 1.2 Goals of the project The objectives of our project is to investigate the Signal Flow Graph (SFG) of the resonator based SDM structure, with realizable delay placement inside the loops of the SDM to avoid the instability of overall design. This can be done in Matlab by using different topologies of the delay placement in the SDM model. Checking the SNR and then go for the circuit realization of the proposed SDM. When the above step is completed, the scaling of the capacitors and output range of the integrators is investigated because without scaling the SDM can not remain stable for longer period of time. ADC and DAC should also be realized at circuit level. 3

16 4 Introduction 1.3 Specifications We are designing the ADC for the WCDMA applications, that usually uses the direct sequence CDMA. In WCDMA the channel separation is 5Mhz per carrier and the signal band width is of 3.84Mhz as shown in Fig 1.1 Figure 1.1. Principle amplitude spectrum of a multicarrier WCDMA signal. The ADC which we design can also be used in the heterodyne receiver architecture shown in Fig 1.2 where a radio frequency (RF) signal is received by the antenna and is then filtered by the bandpass filter and amplified by the Low Noise Amplifier (LNA). The intermediate frequency (IF) signal is given to Voltage Gain Amplifier (VGA). The output of the VGA is then down converted and passed through an anti-aliasing filter. The signal is finally digitized by the ADC which in our case is an SDM and processed by the DSP. The SNR we want to achieve is 80db with a sampling frequency of 320MHz.

17 1.4 Design challenges 5 Figure 1.2. Heterodyne receiver architecture. 1.4 Design challenges The design challenges of our design are as follows: The loop filter in the modulator with optimized coefficients. The circuit realization of the ADC and DAC. OTA design in the modulator. Timing, settling and internal noise in the integrator. Settling time and mismatch errors in the DAC. Power consumption minimization. 1.5 Work flow Our thesis work was performed according to the top down working methodology. The design flow of the thesis work is given below : There were two structures of the SDM 5th order SDM and the 3rd order SDM out of which we had to finalize one for our final design. Noise Transfer Function (NTF) optimization of our SDM. Coefficient calculation of the multipliers in our design. To make the SFG in precedence form. Matlab executable model from the system of equations in computable order.

18 6 Introduction Run the complete model of SDM in matlab and try to achieve the required SNDR. Find the maximum stable input range (MSIR) for which the SDM remains stable, and this will also be done in matlab. Switched capacitor realization of the modulator from a given SFG description. Timing extraction. Circuit level model in Cadence using 0.18µm technology. Dynamic range scaling. Settling error simulations. DC gain simulation. Capacitor size optimization from noise and area perspective. SDM noise budget. OTA design and compensation. Track and hold amplifier design. Switch design. Quantizer design. DAC design. Run the complete schematic model of SDM s in Cadence and try to achieve the required SNDR. The circuit layout. Finally the tape out. 1.6 Limitations Due to the lack of time the circuit realization of the Operational Transconductance Amplifier (OTA), optimization of the capacitors regarding to the area perspective and noise optimization are not performed. The decimation filter which filters the signal after the SDM is out of our scope and finally the switches which we use in our switched capacitor network are ideal.

19 Chapter 2 Sigma-Delta Modulator 2.1 Basic concept of SDM According to Nyquist theory, minimum sampling frequency (fs) to avoid aliasing should be twice the bandwidth of the signal to be digitized. The ratio between sampling frequency and Nyquist frequency is called Over-Sampling Ratio (OSR). By over-sampling, an analog signal with fewer number of bits per sample can be used compared to Nyquist rate ADC. ADCs operated at higher sampling rate than the Nyquist rate also relaxes the specifications of the anti-aliasing filter that is used after the SDM. The name Sigma-Delta is used because it has a differentiator (delta) which takes the difference of the incoming sample and the feed back sample. The higher the order of the loop filter, the more accurate is the feed back sample. The basic block of the SDM is shown in Fig 2.1 with the main building blocks which are, ADC, DAC, integrator and a subtractor. Figure 2.1. First-order sigma-delta modulator with 3-bit quantizer. 7

20 8 Sigma-Delta Modulator The digital output is fed back to the DAC and is subtracted from the input signal, the difference signal is accumulated in the integrator and then quantized by the ADC. The purpose of the DAC is to maintain the average output of the integrator near to the comparator reference level. By summing the error voltage the integrator functions as a low pass filter to the input signal and high pass filter to the quantization noise. 2.2 Oversampling The ratio between the sampling frequency and the nyquist frequency is called the oversampling ratio, with higher OSR the signal band become smaller but the NTF more effective. The OSR thus can be defined as: OSR = F s 2F in (2.1) where Fs is the sampling frequency and Fin is the input signal frequency. To understand the basic concept of oversampling, consider a signal that is sampled at a Fs, according to Nyquist theorum. The Fast Fourier Transform (FFT) analysis where we see a signal and noise extending from DC to Fs/2 shown in Fig 2.2 [3]. Figure 2.2. ADC. FFT analysis showing signal and quantization noise for a Nyquist rate

21 2.3 Noise shaping 9 By increasing the sampling frequency Fs by a factor k, an FFT analysis shows that the noise floor has dropped. SNR is the same as before but noise energy has spread as shown in the Fig 2.3 [3]. In other words SNR is improved within the band of interest. Figure 2.3. FFT analysis illustrating oversampling. 2.3 Noise shaping The advantage of the oversampled ADC is that noise can be shaped at higher frequencies by using oversampling as shown in Fig 2.4 [3]. We can see that by noise shaping the noise energy within the signal band is reduced. The quantization noise of the ADC is highpass filtered to yield low quantization noise in the signal bandwidth (low frequencies), and noise at the high frequencies can be removed by the digital filters before the signal is further processed.

22 10 Sigma-Delta Modulator Figure 2.4. FFT analysis showing shaped noise. The basic advantages of using the SDM over other converters are that the SDM has high speed, good resolution and integration and most important that the implementation cost is low. 2.4 Limitations of SDM The key principle of oversampling in SDM is to trade the bandwidth for the resolution. To increase the signal frequency range one must increase the sampling frequency which also means fast switching and more power. By using a high OSR, the number of quantization bits can be reduced to achieve good SNR. So here we can conclude that there are different trade-offs on the different components in the sigma delta modulator. For low power ADC the accuracy can be traded off and for high speed ADC and to get good SNR the over sampling will be high as well as modulation order. More quantization means more power consumption.

23 Chapter 3 CRFB with feed forward and feed back connections 3.1 Methodology The SDM used in the thesis project is described by the signal flow graph shown in Fig 3.1. Figure 3.1. Third-order SDM with interconnections. This SFG shows the cascade of resonator with distributed feed-forward and feed-back (CRFB) structure for the third-order modulator. Here, X is the input signal and Y is the output signal, Y is also the quantized version of the signal U. For the third-order sigma delta modulator which is shown in Fig 3.1 [4] one can have one or sveral delay elements at m0-m11. There are a lot of combinations for 11

24 12 CRFB with feed forward and feed back connections the delay elements to be placed but one realizable placement of delays which we concluded in our design is shown in Fig 3.2. Figure 3.2. Third-order SDM with placement of delays. In the third-order SDM we have one resonator block and one integrator block, the first integrator has a zero placement at Z = 1, and the resonator with the feedback multiplier coefficient -G1 can be used for adjustable zero placement of the transfer function. NTF is dependent on the coefficients Ai and Gi coefficients. Similarly the signal transfer function (STF) depends on the Ai, Bi and Gi, if there is no feedback structure (Gi are set to zero) then a noise transfer function (NTF) will be highpass and the SDM will be a lowpass. In the SDM it is possible to find the optimized coefficients for the NTF and the STF.

25 3.2 Matlab realization Matlab realization Coefficient calculation for third-order SDM From the structure shown in Fig 3.2 the system of equations are developed to calculate the NTF and STF. After that we optimize the NTF in Matlab, the magnitude response for the NTF and allpass STF are shown in Fig 3.3. Figure 3.3. Magnitude response of the third-order SDM. The multiplier coefficients for the third-order SDM used in the design are given in Table 3.1. Multplier Cofficients A A A G B B B B3 1 Table 3.1. Multiplier cofficients for the third-order SDM.

26 14 CRFB with feed forward and feed back connections The generalized structure of the SDM is shown in Fig3.4 [5] which has been divided in three main parts which are, Loop filter, ADC and DAC. Figure 3.4. General structure of a three bit quantizer sigma-delta modulator The Loop filter here is a system having two inputs X and W therefore U in the Z domain can be express as U(z) = L 0 (z)x(z) + L 1 (z)w (z) (3.1) And similarly the quantizer can simply be modeled as an output plus an error source mathematically can be expressed as Y (z) = U(z) + E(z) (3.2) From the equations (3.1) and (3.2) we can write the output Y(z) as the combination of modulator input and quantization error. Y (z) = X(z)ST F (z) + E(z)NT F (z) (3.3)

27 3.2 Matlab realization 15 The NTF and STF can be realized as NT F (z) = 1 1 L 1 (z) (3.4) ST F (z) = L 0(z) 1 L 1 (z) (3.5) we have NTF and STF realization from the Matlab we can compute the L0 and L1 as L 0 = L 1 = 1 ST F (z) NT F (z) 1 NT F (z) (3.6) (3.7) The DAC and the ADC modules used are assumed to be ideal, it should be noted that the L0 and L1 should be large in the required range because a large L1 reduces the NTF. L0 can be chosen such that STF approximates or equals to unity.this means that L0 and L1 should have poles in the required range, so the L0 and L1 have the same poles but different zero location, this can be shown in the Fig 3.5. Figure 3.5. Pole-zero plot for L0 and L1.

28 16 CRFB with feed forward and feed back connections 3.3 Matlab model of the third-order CRFB SDM The signal flow graph of the SDM shown in Fig 3.2 was modeled in Matlab. For the simulation of the SFG in Matlab the integrator blocks were modeled by an adder and a delay which is shown in Fig 3.6. Figure 3.6. Integrator model for Matlab. The precedence graph of the operations in computable order generated in Matlab is shown in Fig 3.7. Figure 3.7. Precedence graph for third-order SDM.

29 3.3 Matlab model of the third-order CRFB SDM 17 From the graph we can find the equations in computable order. We simulate the model of the SDM by applying a input sinusoid signal at the input X shown in Fig 3.2, the quantizer adds the quantization noise and the integrator acts as a highpass filter to the noise, it shapes the noise towards the high frequencies. The output spectrum of the third-order modulator with three bit quantization and OSR of 32 is shown in Fig 3.8. Figure 3.8. Output spectrum of third-order SDM. The high frequency quantization noise can be removed by a digital lowpass filter without affecting the input signal. This lowpass filter is part of the decimation process and the digital filter at the output is used to get the maximum attenuation only for the higher frequency components keeping the analog input signal unaffected and the shaped noise is attenuated. Finally at the output from the filter, the noise is much flattened as shown in the Fig 3.9.

30 18 CRFB with feed forward and feed back connections Figure 3.9. Filtered signal amplitude spectrum. 3.4 Maximum stable input range The maximum stable input range is the range of the input signal for which the output of the SDM remains stable within the specified SNDR range. For this purpose the sigma-delta modulator of order three is simulated in Matlab for a range of amplitude versus a range of frequencies and SNDR for these ranges was checked. After simulating the third-order SDM for MSIR we obtain the plot shown in Fig Figure SNDR versus input signal amplitudes.

31 3.4 Maximum stable input range 19 Figure MSIR (minimum of the maximum amplitudes). Finally the MSIR is the minimum of the maximum amplitudes for a range of frequencies as shown in Fig 3.11.

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33 Chapter 4 Clocking for SC SDM 4.1 Clock generation module The non-inverting connections or the inverting connections of an SC integrator can be used in the realization of the SC SDM. Such circuits use two phase clocks which means two non-overlapping clocks P1 and P2 generated from the master clock Clk and two additional trigger signals P1a and P2a are constructed out of the non-overlapping clocks, the timing diagram of the trigger signals along with the non-overlapping clock is shown in the Fig 4.1. Figure 4.1. Clock timing diagram The two extra trigger signals P1a and P2a have the difference that these signals go low a little earlier than the clocks P1 and P2. P1a and P2a clocks are used to end the integration phase of the integrator. And also to reduce the charge injection 21

34 22 Clocking for SC SDM in the circuit. The complete transistor level realization of the clock module was implemented and tested for the correct functionality. Fig 4.2 shows the design of the clock generator module [5]. Figure 4.2. Non-overlapping clock generator. The four inverters in Fig 4.2 having a * sign are the one used for non-overlap adjustment. The width of these inverters can be varied for the adjustment of the clock duty cycles. The results obtained from the transistor level realization are shown in Fig 4.3.

35 4.1 Clock generation module 23 Figure 4.3. Clock generator schematics results.

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37 Chapter 5 Switched-capacitor realization of SDM 5.1 Realization from SFG to SC network The design in Fig 5.1 of the third-order SDM with CRFB has to be modeled with a switched-capacitor network. For this the method of equivalence transformations is used in order to have a full delay or a half delay at the input of every integrator. This means that the two integrators will never have to follow each other without some delay in between them and also gives good settling time. Figure 5.1. Third order SDM The delay elements, one after the third integrator and the delay in the feedback path (marked as A in the Fig 4.1) are moved back and transformed into one delay element at each input of the adder three. Then half of the delay element is moved 25

38 26 Switched-capacitor realization of SDM from the output of the second integrator to the three inputs of the second adder. Now we have one and a half delay at the output of the first integrator, out of which half delay element is moved back and now we have half delay elements at each input of the adder one. The final transformed structure having half or a full delay at all integrator inputs used in the design is shown in Fig 5.2. Figure 5.2. Third order SDM with full or half delay at the integrator input. In the SDM model we can design inverting and non-inverting integrators, the general SC integrator structure is shown in Fig 5.3. Figure 5.3. A general integrator model.

39 5.1 Realization from SFG to SC network 27 Figure 5.4. Inverting and non inverting connection. The switch with clock P2a acts as an integration switch and switches with clock P1 as a sampling switch. If node X of the the structure in Fig 5.3 is connected with node Y of the Fig 5.4a, the integrator acts as a non-inverting integrator having a transfer function given in equation (5.1). If the connection X of the structure in Fig 5.3 is connected to the node Z of the Fig 5.4b the integrator acts as an inverting integrator having a transfer function shown in equation (5.2) Z 1 V out(z) = C 1 ( )V in(z) (5.1) C 2 1 Z 1 Z 1 2 V out(z) = C 1 ( )V in(z) (5.2) C 2 1 Z 1

40 28 Switched-capacitor realization of SDM The integrator in the SDM design having either a full or a half delay at the input can be clocked in different ways. For example we take the first integrator of the SDM as shown in Fig 5.2. As both of the inputs are inverting the structure of the switched capacitor integrator having two inverting inputs with proper switching of the clocks is shown in Fig 5.5. Figure 5.5. Integrator with two inverting inputs. The integrator realized in Fig 5.5 has two inverting inputs. The input controlled by the switches that have P2 as a trigger are conducting in integration phase of the integrator.by applying charge analysis and charge conservation methods, the transfer function can be calculated as given in equation (5.3). Z 1 2 Z 1 2 V out(z) = C 1 ( C 3 1 Z 1 )V 1(z) C 2 ( )V 2(z) (5.3) C 3 1 Z 1 As both the inputs of the integrator are inverting, this results in a negative sign at the output and an integration with a half unit delay.

41 5.1 Realization from SFG to SC network 29 We also flip the input signals Xin+ and Xin- in differential circuit in order to compensate for the negative sign with voltage V1(z) in equation (5.3) For a certain case when one of the inputs is inverting and the other is noninverting the structure of the switched capacitor integrator having one inverting and one non inverting input with proper switching of the clocks is shown in Fig 5.6. Figure 5.6. Integrator having one inverting and one non inverting input. The integrator realized in Fig 5.6 has one inverting and one non-inverting input. The input controlled by the switches that have P2 as a trigger are conducting in integration phase of the integrator and the switches triggered by P1 are conducting in the sampling phase of the integrator. Similarly by applying charge analysis and charge conservation methods, the transfer function can be calculated as given in equation (5.4). Z 1 Z 1 2 V out(z) = C 1 ( C 3 1 Z 1 )V 1(z) C 2 ( )V 2(z) (5.4) C 3 1 Z 1 As one of the inputs of the integrator is non-inverting, this results in a postive sign at the output and an integration with a full delay. Also a negative sign with a half unit delay because of the inverting input. In the same way we can model the rest of the circuit having other combinations of a full delay or a half delay at the input of the integrator. The fully differential circuit implementation of the third order SDM in Fig 4.2 is given in Fig 5.7.

42 30 Switched-capacitor realization of SDM Figure 5.7. Fully differential SC CRFB network

43 Chapter 6 OTA modeling for SDM 6.1 Small signal model For circuit realization of the sigma-delta modulator one needs to set the requirements of the OTA to be used in the switched-capacitor network. The important parameters to be considered are phase margin, DC-gain, output range, slew-rate and unity gain bandwidth. To design a high performance SC network one needs the optimization of the components. The integrator model used in the third-order sigma-delta modulator is shown in Fig 6.1. Figure 6.1. SC integrator with several inputs. This realization of the integrator is mapped into a return ratio model [1] which is shown in Fig

44 32 OTA modeling for SDM Figure 6.2. Return ratio model of the SC integrator. The feedback factor beta is defined as as β = V op Ch = V out Cs + Ch (6.1) From Fig 6.1, the integrator having more inputs, the feed-back factor β is given β = V op V out = n Ch (Cn + Ch) (6.2) To obtain certain requirements of the OTA we use a two-pole model of the OTA as shown in Fig 6.3. Figure 6.3. Two pole small signal model

45 6.1 Small signal model 33 The transfer function of the two pole model is given as H(s) = V out(s) V in(s) = R 1 gm 1 R 2 gm 2 (1 + R 1 C 1 s)(1 + R 2 C 2 s) (6.3) The DC-gain A0 of the above model is given as A 0 = R 1 gm 1 R 2 gm 2 (6.4) The frequency of the first pole and the second poles are given as The pole separation factor is defined as ω1 = 1 R 1 C 1 (6.5) ω2 = 1 R 2 C 2 (6.6) γ = ω2 ω1 (6.7) Using equations (6.4), (6.5), (6.6), (6.7) we obtain γ can be calculated as H(s) = V out(s) V in(s) = A 0 (1 + s ω1 )(1 + s γω1 ) (6.8) γ = 4(1 + A 0β) 1 + ( π lnd )2 (6.9)

46 34 OTA modeling for SDM In equation (6.9), D is the error bound which is the maximum settling error tolerated in the design so that the specific requirements on the SNR are met. To find the error bound, random error sources are introduced after every integrator in the SDM design as shown in Fig 6.4. Figure 6.4. SFG with error sources used to simulate SNDR degradation due to incomplete settling. After introducing the error sources we need to know the maximum settling error tolerated in the design so that the requirements on the SNR are met, for this purpose the SDM design is simulated in Matlab such that the SNR is not degraded below the desired values. The plots are obtained for SNDR limit versus the error bound in order to get the value for the error bound which is shown in Fig 6.5. Figure 6.5. SNDR vs Error bound.

47 6.1 Small signal model 35 From the simulations in Matlab the settling error bound D is 10 4 for the system having an SNDR of 80 db. For finding the phase margin (PM) for minimum settling time (MST) as described in [1] with a specified feedback factor β and an error bound D is given as φ MST = 90 o tan 1 [ 1 + (πlnd) ] (6.10) 4β

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49 Chapter 7 Analog to digital converter 7.1 Introduction Our real world is analog and the analog quantities can be weight, time voltage etc. In the digital domain we have ones or zeros, the analog signals are converted into digital signals in proportion to its analog value by analog to digital converters (ADC). There are two main processes in the conversion. One is the sampling and other is the quantization. During sampling, the analog signal is divided in to discrete time samples with a sampling frequency Fs. This sampled data is then quantized to N discrete levels or 2 N number of bits. By increasing the number of bits more accuracy is achieved. If the sampling rate is equal to twice the bandwidth of the signal then these are called the Nyquist rate ADC s. Oversampled ADC s with a sampling rate more than the Nyquist rate can be used with fewer number of bits per sample. 7.2 Resolution of ADC The maximum number of discrete values an ADC can produce is the resolution of an ADC. These values are usually in a binary form and the resolution of the ADC is normally expressed in N bits with 2 N number of different levels for the analog input signal. The least significant bit is represented by V LSB = V ref and 2 N Vref is the input range of the analog signal. The larger the number of bits the higher the number of levels and also the higher the resolution of the ADC. 37

50 38 Analog to digital converter 7.3 Quantization After the sampling of the analog signal each sample is quantized to a discrete value corresponding to the analog value of input signal. The quantization introduces an error which is called the quantization error. 7.4 Architecture There are different types of ADC architectures depending on the different applications and requirements. Some of the architectures are flash ADC, successive approximation ADC, ramp compare ADC, pipelined ADC etc. The architecture we use in our project is flash ADC with N bits resolution, 2 N quantization levels, and 2 N -1 comparators, where N = 3. The realization of the 3-bit quantizer is shown in Fig 7.1. The output produced by the comparator is thermometric coded. This thermometric code is converted into binary format as shown in Table 7.1 by a thermometric to binary decoder. Figure 7.1. Three-bit flash ADC with decoder. The problem with the ADC architecture is that as the number of bits increases, the number of comparators also increases rapidly and the therefore the hardware

51 7.5 Behavioral level design 39 increases as well so the number of bits is limited to 10 to avoid the huge power consumption and area of a chip. Another problem of using a large number of comparators is the large input capacitance so the circuits driving the ADC s must be able to drive the large capacitive load. Therefore, the flash ADC is not suitable where one need high resolution. Thermometer Binary Table 7.1. Thermometer to binary code. 7.5 Behavioral level design The ADC implemented in our design is a 3-bit flash ADC. The output of the ADC is a thermometric coded value. At behavioral level ADC was implemented by using the VerilogA code. 7.6 Circuit realization As the ADC is clocked, we are using four clocks in our overall design P1, P1a, P2, P2a which are derived from the clock generation module. The ADC is working on the rising edge of the clock P1. The input is differential and the range of the ADC is determined by the reference voltage Vref. The ADC consist of three submodules which are the comparator, the inverter chain, the SR-latch Comparator The comparator is a differential component which compares the differential input to the comparator with the reference voltages as shown in Fig 7.2. The ADC works on the rising edge of the clock so, when the clock is low the pull down network is disconnected from the output while the output nodes are equalized and when the clock goes high (in the evaluation mode) current starts to flow in the pull down network. As one of the input is higher (Vinp with Vrefp, or Vinn with Vrefn or vise versa ) more current flows in those transistors. For example if Vinp is greater, more current flows in the transistors which is connected to V1 as shown in Fig 7.2 and achieve its threshold level and switch.

52 40 Analog to digital converter Figure 7.2. Comparator schematics Inverter and SR-latch At the output of the comparator the inverter chain (minimum of two inverters) is used so that the output stabilizes either to one or zero. The SR-latch shown in Fig 7.3 is used because if the comparator produces some wrong value when the pull down network is disconnected (in equalization mode) the SR-latch then keeps the previous value.

53 7.6 Circuit realization 41 Figure 7.3. The SR-latch Simulation results of ADC For simulation purposes a test bench to check the functionality of the ADC was developed which is shown in Fig 7.4. Figure 7.4. Test bench for the ADC.

54 42 Analog to digital converter Here the ADC converts the two signals into thermometric code. Vrefn and Vrefp are the reference level for the ADC. The thermometric code is converted into binary by thermometric encoder. The results obtained from the schematic design of ADC are shown in Fig 7.5. Figure 7.5. Simulation results of ADC schematic design.

55 Chapter 8 Digital to analog converter 8.1 Introduction A digital-to-analog converter is a device which converts the digital signal (binary, thermometric code etc.) to analog signal (voltage or current). The SDM loop, the signal from the ADC which is thermometric code is converted into analog by the DAC, and is then fed back in the SDM loop. The DAC generates differential output signals. The purpose of the feedback DAC is to maintain the average output of the integrator near the comparator s reference level. 8.2 Behavioral level design The DAC implemented in our design is a switched-capacitor DAC [2]. At behavioral level this is implemented by using the VerilogA code for the switches while keeping the schematic version for capacitors. 8.3 Circuit realization The schematic design of the DAC along with the clock signals was made at transistor level. Fig 8.1 shows the the architecture of DAC element [2]. These DAC elements are connected together as shown in Fig 8.2 to get a fully differential output that is DACout+ and DACout-. 43

56 44 Digital to analog converter Figure 8.1. Architecture of DAC element. Figure 8.2. SC DAC structure for the SDM.

57 8.4 Simulation results 45 Figure 8.3. Test bench setup to check the functionality of the DAC 8.4 Simulation results For simulation purposes a test bench to check the functionality of the DAC was developed which shown in Fig 8.3. Here two differential signals Vinn and Vinp are the input to the system the ADC converts the two signals into thermometric code. The DAC converts this code to the analog value. The range of the DAC is defined by the Vrefn Vrefp. The common-mode voltage is defined by the Vcmo signal. The Dacoutp and Dacoutn are the two output ports from where we get the corresponding differential analog signal out. The schematic design of the DAC having ideal switches was tested for correct functionality. The results of the simulation of the DAC are shown in Fig 8.4.

58 46 Digital to analog converter Figure 8.4. Simulations results from the schematic of DAC.

59 Chapter 9 Results 9.1 Results SC realization of the SDM structure The thesis work explains the top down approach to model the the SDM stuucture, optimization of the coefficients of the NTF and the STF, optimizing the multiplier coefficients of the higher order resonator structure of the SDM s and then model the SFG in matlab and find the results. In the thesis work we try to explain the step by step method of modeling SDM design with CRFB modulator structure to a fully differential switch capacitor realization. The method to use inverting and non inverting SC integrator were explained. In the thesis work we also suggested the fully differential architectures of the ADC, SC DAC and an on-chip clock generation module OTA modeling To design a high performance and a good low power design of the SDM it is very important to optimize the requirements for the OTA, as it is the main source of power consumption of the SDM design. Due to shortage of time we were not able to develop more test benches to fully optimize output range, slew rate and unity gain bandwidth for the OTA. In the thesis work we realized the OTA model with differential two-pole resistor capacitor model. 47

60 48 Results 9.2 Simulation results Matlab model results The third-order design of the SDM in Fig 3.2 with optimized multiplier coefficients was modeled in Matlab. Precedence graph was made made in order to get the equations in computable order. The quantizer used in the design is a three-bit quantizer. The maximum stable input range which is the range of the input signal for which the output of the SDM remains stable was determined which came out to be This value of the maximum input amplitude was used in SDM simulation in Matlab. The output spectrum of the third-order modulator with three-bit quantization and OSR of 32 is shown in 9.1. Figure 9.1. Output spectrum of the third-order modulator. Finally the signal to noise and distotion ratio (SNDR) and the effective number of bits (ENOB) were calculated. The SNDR calculated for the third order SDM design was dB and ENOB =

61 9.2 Simulation results Cadence model results After the Matlab realization of the SDM, an executable model in cadence using 0.18 micron technology was made. In the first stage test benches of all the main blocks like ADC, DAC, clock module were made and tested. The results showing the correct functionality of every block have been shown in the previous chapters. For simulation purposes a test bench to check the functionality of the complete model of the SDM was developed which is shown in Fig 9.2. Figure 9.2. Test bench for the third-order CRFB SDM. Here two differential signals Vinn and Vinp, with input frequency of 5 MHz and a common mode level of Vcmo are the input to the third-order SDM. The output from the integrators is fed to a 3-bit flash ADC which coverts from analog signal to its corresponding thermometer code. This code is converted into binary by the encoder. The DAC converts this code to the analog value and the range of the DAC is defined by the Vrefn, Vrefp, and the common mode voltage is defined by the Vcmo signal. The out from the DAC is fed back to the SDM loop. The digital ouput from the ADC is stored in a file through a File write block. This data is read into the Matlab where one can find the SNDR and ENOB. The output spectrum of the signal read in Matlab is shown in 9.3.

62 50 Results Figure 9.3. Simulation results from cadence model. The SNDR calculated for the third-order SDM design with an input signal of 5 MHz and a sampling frequency of 320 MHz, having OSR=32 was dB and ENOB =

63 Bibliography [1] T.Fiez Chilakapati. Settling time considerations for sc integrators. Circuit and Systems Vol. 1, 31pp [2] Ian Galton. Delta- sigma data convertion in wireless transceivers. Microwave theory and techniques, vol [3] MAXIM. Delta, a/d and d/a conversion/sampling circuits. [4] Krister Berglund Oskar Matteusson. On the realization of switch capacitor integrators for sigma delta modulators. [5] G. Temes R. Schreier. Understanding Delta-Sigma Data Converters. 51

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