Institutionen för systemteknik

Institutionen för systemteknik Department of Electrical Engineering Examensarbete A Continuous-Time ADC and DSP for Smart Dust Examensarbete utfört i Elektroniksystem vid Tekniska högskolan vid Linköpings universitet av Dhurv Chhetri, Venkata Narasimha Manyam LiTH-ISY-EX--11/4436--SE Linköping 2011 Department of Electrical Engineering Linköpings universitet SE-581 83 Linköping, Sweden Linköpings tekniska högskola Linköpings universitet 581 83 Linköping

A Continuous-Time ADC and DSP for Smart Dust Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping av Dhurv Chhetri, Venkata Narasimha Manyam LiTH-ISY-EX--11/4436--SE Handledare: Examinator: Niklas U Andersson isy, Linköpings universitet J Jacob Wikner isy,linköpings universitet J Jacob Wikner isy, Linköpings universitet Linköping, 31 May, 2011

Avdelning, Institution Division, Department Division of Electronics Systems Department of Electrical Engineering Linköpings universitet SE-581 83 Linköping, Sweden Datum Date 2011-05-31 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport ISBN ISRN LiTH-ISY-EX--11/4436--SE Serietitel och serienummer Title of series, numbering ISSN URL för elektronisk version http://www.es.isy.liu.se http://www.es.isy.liu.se Titel Title A Continuous-Time ADC and DSP for Smart Dust Författare Author Dhurv Chhetri, Venkata Narasimha Manyam Sammanfattning Abstract Recently, smart dust or wireless sensor networks are gaining more attention. These autonomous, ultra-low power sensor-based electronic devices sense and process burst-type environmental variations and pass the data from one node (mote) to another in an ad-hoc network. Subsystems for smart dust are typically the analog interface (AI), analog-todigital converter (ADC), digital signal processor (DSP), digital-to-analog converter (DAC), power management, and transceiver for communication. This thesis project describes an event-driven (ED) digital signal processing system (ADC, DSP and DAC) operating in continuous-time (CT) with smart dust as the target application. The benefits of the CT system compared to its conventional counterpart are lower in-band quantization noise and no requirement of a clock generator and anti-aliasing filter, which makes it suitable for processing burst-type data signals. A clockless EDADC system based on a CT delta modulation (DM) technique is presented. The ADC output is digital data, continuous in time, known as data token. The ADC employs an unbuffered, area efficient, segmented resistor-string (R-string) feedback DAC. A study of different segmented R-string DAC architectures is presented. A comparison in component reduction with prior art shows nearly 87.5% reduction of resistors and switches in the DAC and the D flip-flops in the bidirectional shift registers for an 8-bit ADC, utilizing the proposed segmented DAC architecture. The obtained SNDR for the 3-bit, 4-bit and 8-bit ADC system is 22.696 db, 30.435 db and 55.73 db, respectively, with the band of interest as 220.5 khz. The CTDSP operates asynchronously and process the data token obtained from the EDADC. A clock-less transversal direct-form finite impulse response (FIR) low-pass filter (LPF) is designed. Systematic top-down test-driven methodology is employed through out the project. Initially, MATLAB models are used to compare the CT systems with the sampled systems. The complete CTDSP system is implemented in Cadence design environment. The thesis has resulted in two conference contributions. One for the 20th European Conference on Circuit Theory and Design, ECCTD 11 and the other for the 19th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 11. We obtained the second-best student paper award at the ECCTD. Nyckelord Keywords smart dust, Event-driven( ED), continuous time(ct), Delta-modulation(DM), segmented register string Digital to analog converter (DAC), digital signal processing (DSP)

Abstract Recently, smart dust or wireless sensor networks are gaining more attention. These autonomous, ultra-low power sensor-based electronic devices sense and process burst-type environmental variations and pass the data from one node (mote) to another in an ad-hoc network. Subsystems for smart dust are typically the analog interface (AI), analog-to-digital converter (ADC), digital signal processor (DSP), digital-to-analog converter (DAC), power management, and transceiver for communication. This thesis project describes an event-driven (ED) digital signal processing system (ADC, DSP and DAC) operating in continuous-time (CT) with smart dust as the target application. The benefits of the CT system compared to its conventional counterpart are lower in-band quantization noise and no requirement of a clock generator and anti-aliasing filter, which makes it suitable for processing burst-type data signals. A clockless EDADC system based on a CT delta modulation (DM) technique is presented. The ADC output is digital data, continuous in time, known as data token. The ADC employs an unbuffered, area efficient, segmented resistorstring (R-string) feedback DAC. A study of different segmented R-string DAC architectures is presented. A comparison in component reduction with prior art shows nearly 87.5% reduction of resistors and switches in the DAC and the D flipflops in the bidirectional shift registers for an 8-bit ADC, utilizing the proposed segmented DAC architecture. The obtained SNDR for the 3-bit, 4-bit and 8-bit ADC system is 22.696 db, 30.435 db and 55.73 db, respectively, with the band of interest as 220.5 khz. The CTDSP operates asynchronously and process the data token obtained from the EDADC. A clock-less transversal direct-form finite impulse response (FIR) low-pass filter (LPF) is designed. Systematic top-down test-driven methodology is employed through out the project. Initially, MATLAB models are used to compare the CT systems with the sampled systems. The complete CTDSP system is implemented in Cadence design environment. The thesis has resulted in two conference contributions. One for the 20th European Conference on Circuit Theory and Design, ECCTD 11 and the other for the 19th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 11. We obtained the second-best student paper award at the ECCTD. v

Acknowledgments First of all, we would like to thank our supervisor and guru, Dr. J Jacob Wikner, for introducing us to the exciting research field of CTDSPs and tutoring us mixedsignal processing systems, in our master s program. We were always inspired by his style and approach. We would like to offer our sincerest gratitude to him for guiding us throughout the thesis with his knowledge and patience and also providing space to think in our own way. It would not have been possible to complete the thesis project work and write the conference papers without his support. One simply could not wish for a better or friendlier supervisor. We are also extremely thankful to Niklas U Andersson for his expert knowlege and supervision. We would like to thank all the professors and Ph.D. students at the division of Electronics Systems, Department of Electrical Engineering, Linköping University, especially to Joakim Alvbrant, for extending some quick support to resolve design issues and challenges related to simulations. We also thank our thesis opponents Sajib Roy and Murad Kabir Nipun for their time and invaluable feedback on the thesis. A very special thanks to all our colleagues in master thesis lab (signal och bild), especially to Sheheryar, Asfandyar and Tanvir, for helpful discussions and suggestions in many practical issues of design and documentation. We would like to thank Mariya Kurchuk, Ph.D. Student, Columbia University for taking time from her busy schedule to reply to our smallest query with great details. We thank all people, who are directly or indirectly involved in the completion of this thesis, whose names that we might have forgotten to mention here. I (Dhurv Chhetri) would also like to thank Sanjiv Bhakhura, Navneet Agarwal, Santosh Joshi, Amit Sundariyal, Rajeev Kharbanda and Chetan Rao for continuous support and inspiration. I (Venkata Narasimha Manyam) would also like to thank Sarath, Suresh, Lokesh and Dinakar for being my friends and inspiring me. Lastly, we would like to show our sincere gratitude towards our beloved parents and family members, who have always believed in us and we thank for their unconditional support, love and affection. vii

Contents 1 Introduction 7 1.1 Smart dust: A brief introduction................... 7 1.2 Smart dust: specification....................... 8 1.3 Continuous time processing...................... 9 1.4 Thesis organization........................... 9 2 Conventional versus Event-driven systems 11 2.1 Conventional clocked DSP systems.................. 11 2.1.1 Introduction.......................... 12 2.1.2 Operational details....................... 13 2.1.2.1 Sampling, quantization and digital encoding... 13 2.1.2.2 Digital signal processing and reconstruction.... 15 2.1.3 Advantages........................... 16 2.1.4 Drawbacks........................... 17 2.2 Continuous-time or event-driven DSP systems............ 18 2.2.1 Introduction.......................... 18 2.2.2 Operational details....................... 19 2.2.2.1 Level-crossing quantization technique....... 19 2.2.2.2 Processing of CT digital data and reconstruction. 20 2.2.3 Advantages........................... 21 2.2.4 Drawbacks........................... 22 2.3 Conventional DSP versus CTDSP: A comparison.......... 24 2.4 Conclusion............................... 24 3 Sub module details for the CTDSP systems 25 3.1 Event-driven ADC........................... 25 3.1.1 Mid-tread vs mid-rise quantizers............... 26 3.1.2 Properties of mid-tread quantizers.............. 27 3.1.3 Level-crossing sampling for the CTADC........... 28 3.1.3.1 Amplitude quantization in the CTADC...... 29 3.1.3.2 Time and frequency domain analysis of the CTADC quantizer....................... 29 3.1.4 Comparison of different ADC architectures......... 35 3.1.4.1 Event-driven flash ADC............... 35 ix

x Contents 3.1.4.2 Event-driven delta-modulation ADC........ 36 3.1.5 Summary of event-driven ADC system........... 38 3.2 CTDSP................................. 38 3.2.1 Comparison of CTDSP FIR filter architectures....... 38 3.2.1.1 Event-driven FIR filter with pulse code modulation technique....................... 38 3.2.1.2 Event-driven FIR filter with delta-modulation technique......................... 40 3.2.2 Design consideration of CTDSP system........... 42 3.2.2.1 Transfer function and frequency response of the CTFIR filter..................... 42 3.2.2.2 Minimum distance between consecutive data tokens 43 3.2.2.3 Significance of the granularity constraint on system design......................... 44 3.2.2.4 FIR filter power consumption............ 45 3.2.3 Summary of CTDSP...................... 46 3.3 CTDAC................................. 46 3.3.1 Summary of CTDAC...................... 47 3.4 Conclusion............................... 47 4 Event-driven delta modulation based analog-to-digital converter 49 4.1 Introduction to the event-driven DMADC.............. 49 4.2 Comparator............................... 50 4.3 Asynchronous digital control logic.................. 50 4.3.1 Control logic: Principle of operation............. 50 4.3.2 Control logic: behavioral model, schematic and test results 52 4.3.2.1 Control logic behavioral model........... 52 4.3.2.2 Test bench for control logic behavioral model... 53 4.3.2.3 Control logic schematic............... 55 4.3.2.4 Control logic schematic test results........ 55 4.4 Feedback DAC............................. 55 4.4.1 CTDAC architectures..................... 56 4.4.1.1 Resistor-string DAC................. 57 4.4.1.2 Segmented resistor-string DAC........... 58 4.4.1.3 Segmented resistor-string DAC with buffer amplifier 59 4.4.1.4 Segmented resistor-string DAC with LSB compensation resistor in the MSB string.......... 60 4.4.1.5 Segmented resistor-string DAC with extra resistor in the MSB string.................. 62 4.4.1.6 Segmented resistor-string DAC with the shared MSB resistor........................ 64 4.4.2 Feedback DAC: schematic and test results.......... 66 4.4.2.1 MSB switch resistance compensation technique.. 66 4.4.2.2 Test bench and test results for the 3-bit resistorstring DAC...................... 67

Contents xi 4.4.2.3 Test results for the 4-bit 4 4 segmented resistorstring DAC...................... 70 4.4.2.3.1 With the LSB compensation resistance. 70 4.4.2.3.2 With shared MSB resistance....... 71 4.5 Bi-directional shift registers...................... 71 4.5.1 Bi-directional SR for resistor-string DAC: Principle of operation............................... 71 4.5.2 Bi-directional SR for resistor-string DAC: behavior model, schematics and test results.................. 73 4.5.3 Bi-directional SR for segmented resistor-string DAC: Principle of operation........................ 73 4.5.4 Bi-directional SR for segmented resistor-string DAC: behavior model, schematics and test results............ 73 4.6 Conclusion............................... 75 5 Event-driven digital signal processing 79 5.1 Introduction to CT DSP........................ 79 5.2 Derivation of coefficients for the low-pass filter........... 81 5.3 Delay taps and delay cells....................... 82 5.4 Accumulator/ multiplier block.................... 83 5.4.1 Accumulator/ multiplier block test results.......... 85 5.5 Continuous-time adder block..................... 86 5.5.1 Adder timing control logic................... 86 5.5.2 CT adder block......................... 87 5.6 Output flip-flops............................ 89 5.7 DSP system integration and results.................. 89 5.8 Conclusion............................... 89 6 Event-driven digital-to-analog converter 93 6.1 Output DAC architecture....................... 93 6.1.1 Overall integration of the output DAC............ 93 6.1.2 Digital delta-modulator or the change detector....... 94 6.1.3 Output segmented resistor-string DAC............ 96 6.2 Testbench and the test results for output CTDAC......... 96 6.2.1 Testbench and the test results for the direction logic.... 97 6.2.2 Digital DM test bench and the test results.......... 98 6.2.3 Output DAC test bench and test results........... 101 6.2.4 Conclusion........................... 102 7 CTDSP system: Integration of sub-systems and results 103 7.1 CTADC integration.......................... 103 7.1.1 Component comparison for different ADC architectures.. 103 7.1.2 3 bit-ctadc with the resistor-string feedback DAC.... 105 7.1.3 4-bit CTADC with segmented resistor-string DAC..... 110 7.1.4 8-bit CTADC with segmented resistor-string DAC..... 111 7.1.5 Test results for CTADC system................ 114

xii Contents 7.2 CTDSP system: Overall integration................. 114 7.3 CTDSP system test results...................... 116 7.3.1 3-bit CTDSP system test results............... 116 7.3.2 4-bit CTDSP system test results............... 116 7.4 Conclusion............................... 117 8 Conclusion and future work 121 Bibliography 125 A Appendix A MATLAB codes 129 A.1 MATLAB code used for calculation of CT quantizer in-band SHDR for varying resolution and harmonics................. 129 A.2 MATLAB code used for SNDR calculation of ADC for 8-bit system 131 B Appendix B - Verilog-A Codes 133 B.1 Verilog-A code for 16 16 bi-directional SR............. 133 B.2 Verilog-A code for one shot sub-module............... 136

List of Figures 1.1 Block diagram of a typical smart dust mote.............. 8 2.1 Block diagram of the conventional clocked DSP system....... 12 2.2 Conventional clocked DSP system with the basic building blocks ADC-DSP-DAC............................. 13 2.3 Sampling and quantization in conventional clocked DSP system.. 14 2.4 Sampling, quantization and 3-bit output representation of conventional clocked DSP system....................... 15 2.5 Block diagram of the continuous-time DSP system.......... 18 2.6 CTDSP system with the basic building blocks CTADC-CTDSP- CTDAC.................................. 19 2.7 Level-crossing quantization technique in CTDSP system....... 20 2.8 Level-crossing quantization for a faster input signal......... 22 3.1 Block diagram of AI and CTADC................... 25 3.2 Mid-tread vs mid-rise quantizers.................... 26 3.3 Input-output characteristic of the 3-bit mid-tread quantizer.... 27 3.4 Level-crossing quantization in the CTADC with 3-bit output representation................................. 29 3.5 Input-output waveforms for the 3-bit mid-tread CT quantizer.... 31 3.6 Frequency spectrum of a 3-bit mid-tread CT quantizer....... 32 3.7 Quantization error of a 3-bit mid-tread CT quantizer........ 32 3.8 Frequency spectrum of an 8-bit CT quantizer............. 33 3.9 Frequency spectrum of an 8-bit sampled quantizer.......... 33 3.10 In-band SHDR for an 8-bit CT quantizer with a varying input amplitude.................................. 34 3.11 In-band SHDR improvement for CT quantizer over sampled quantizer with varying ADC resolution................... 35 3.12 In-band SHDR for a CT quantizer with varying ADC resolution and the in-band harmonics....................... 36 3.13 Event-driven ADC based on delta modulation technique....... 37 3.14 Event-driven FIR filter with PCM encoding technique........ 39 3.15 Event-driven FIR filter with up-down counter based DM encoding technique................................ 40 3.16 An ED FIR filter with accumulator/multiplier based DM encoding technique................................. 41 4.1 An event-driven DM ADC....................... 50 4.2 The block diagram of asynchronous digital control logic....... 51 4.3 Testbench for control logic block.................... 53 4.4 Test results for the behavioral model for the control logic block... 54 4.5 Test results of the schematic of the control logic block........ 56 4.6 Voltage distribution for V T op (t) and V Bot (t) as obtained with the resistor-string DAC........................... 57

2 Contents 4.7 Block diagram of the bi-directional SR and CTDAC for the case of resistor-string DAC architecture.................... 58 4.8 Block diagram of the m n segmented resistor-string DAC with the m and n bits Bi-directional SRs.................... 59 4.9 Resistor-string segmented DAC architecture............. 60 4.10 Resistor-string segmented DAC with an isolation buffer....... 61 4.11 Resistor-string segmented DAC with the LSB compensation resistance................................... 62 4.12 Resistor-string segmented DAC with an extra resistor in MSB string. 63 4.13 Resistor-string segmented DAC with the shared resistor in MSB string................................... 65 4.14 MSB switch resistance compensation technique in LSB compensation DAC architecture.......................... 66 4.15 MSB switch resistance compensation technique in shared resistor DAC architecture............................ 67 4.16 3-bit resistor-string DAC schematic.................. 68 4.17 3-bit resistor-string DAC test bench.................. 68 4.18 3-bit resistor-string DAC test results.................. 69 4.19 4-bit 4 4 segmented DAC with compensation resistor test results. 70 4.20 4-bit 4 4 segmented DAC with compensation resistor output with offset during MSB transition...................... 71 4.21 4-bit 4 4 segmented DAC with the shared MSB resistor test results. 72 4.22 Bi-directional SR current and previous output states for resistorstring architecture............................ 72 4.23 4-bit 4 4 bi-directional SR schematic................ 74 4.24 Test-bench used for the simulation of the bi-directional SR..... 75 4.25 Simulation results of the schematic of the bi-directional SR for the case of 4-bit............................... 76 4.26 Output states of the two bi-directional SRs for a 4-bit case, when the direction is high........................... 76 4.27 Schematic of the bi-directional SR for the case of 8-bit........ 77 4.28 Simulation results of the schematic of the two bi-directional SRs used for the case of 4-bit segmented resistor-string DAC....... 78 5.1 Block diagram of the FIR filter..................... 80 5.2 Magnitude response and phase response of the 16 tap transversal FIR filter................................. 82 5.3 Delay cell operation........................... 83 5.4 Accumulator multiplier block diagram................. 84 5.5 Accumulator/multiplier block test bench............... 85 5.6 Simulation output results of the acc/mul block for the two different cases of RCA addition time and matched delay............ 86 5.7 Block diagram of adder timing control logic.............. 87 5.8 CT adder for the final addition..................... 88 5.9 CT DSP system integration....................... 89 5.10 Simulation results of the DSP, showing few major control signals.. 90

Contents 3 6.1 Block diagram of the output CTDAC................. 94 6.2 Block diagram of the digital DM.................... 94 6.3 Direction logic for the digital DM................... 96 6.4 Output DAC architecture........................ 97 6.5 Direction logic test bench........................ 97 6.6 Direction logic test results....................... 98 6.7 Digital DM test bench with ramp input................ 99 6.8 Digital DM test results with ramp input................ 99 6.9 Digital DM test bench with sinusoidal input............. 100 6.10 Digital DM test result with sinusoidal input............. 100 6.11 Output CTDAC test bench with a sinusoidal input......... 101 6.12 Output CTDAC test results with sinusoidal input.......... 101 7.1 Percentage reduction in resistor, switches and the D flip-flop between this work to Schell et al. [5] for different ADC resolutions.. 104 7.2 Schematic of 3-bit ED ADC...................... 105 7.3 Testbench for 3-bit ADC........................ 107 7.4 Effect of noise in a 3-bit ADC system................. 108 7.5 Simulation results for 3-bit mid-tread ADC with resistor-string feedback DAC................................ 108 7.6 3-bit ADC output with input applied with a DC shift of /2... 109 7.7 Output spectrum for 3-bit system with 100 khz band of interest.. 109 7.8 Simulation results for 4-bit ADC with 4 4 segmented resistor-string feedback DAC.............................. 110 7.9 4-bit ADC output with input applied with a DC shift of /2... 111 7.10 Output spectrum for the 4-bit system with 100 khz band of interest.112 7.11 4-bit DAC mismatch simulation results................ 112 7.12 8-bit ADC output with Verilog-A model of each block........ 113 7.13 Output frequency spectrum of an 8-bit DM ADC with 20.416 khz input frequency and 220 khz band of interest............. 114 7.14 Block diagram of the overall CTDSP system............. 115 7.15 Transient response of a 3-bit system.................. 117 7.16 Output spectrum for 3-bit CTDSP system.............. 118 7.17 Transient response of a 3-bit system with a 12 khz input frequency. 118 7.18 Transient response of the 4-bit system................. 119 7.19 Output spectrum of the 4-bit CTDSP system............. 119

4 Contents List of Tables 1.1 CTDSP system specification...................... 9 2.1 Signal description for the clocked DSP system............ 12 2.2 Signal description for the clocked DSP system with an ADC-DSP- DAC sub-systems............................ 13 2.3 Signal description for CT system................... 18 2.4 Signal description for the CTDSP system with the CTADC-CTDSP- CTDAC sub-systems.......................... 19 2.5 Conventional DSP versus CTDSP: A comparison.......... 23 4.1 Test bench parameters for the control logic block........... 53 4.2 Initial delay setting of Inc and Dec pulses for control logic test bench. 54 4.3 Standard cell library gates used in the control logic schematic... 55 4.4 3-bit DAC test bench parameters.................... 69 5.1 The transversal FIR low-pass filter specifications........... 81 5.2 The tap coefficients of the sixteen tap transversal FIR low-pass filter. 81 6.1 Truth table for the output of the direction logic........... 95 7.1 Comparison of the component reduction in this work and Schell et al. [5]................................... 104 7.2 Comparison of the components for 3-bit and 4-bit ADC systems.. 105 7.3 Total delay cells required for the 3-bit, 4-bit and 8-bit system.... 105 7.4 Test setup parameters for a 3-bit ADC system............ 106 7.5 Description of the signals present in the ADC system........ 106 7.6 Test setup parameter for the 4-bit ADC system........... 110 7.7 Test setup parameter for an 8-bit ADC system............ 112 7.8 SNDR and ENOB for 3-bit, 4-bit and 8-bit ADC system...... 114 7.9 SNDR, SFDR and ENOB for the 3-bit and 4-bit CTDSP system.. 117

Contents 5 Acronyms AI ADC DSP DAC RF CMOS ED CT Analog Interface Analog-to-Digital Converter Digital Signal Processor Digital-to-Analog Converter Radio Frequency Complimentary Metal Oxide Semiconductor Event-Driven Continuous-Time CTADC Continuous-Time Analog-to-Digital Converter CTDAC Continuous-Time Digital-to-Analog Converter CTDSP Continuous-Time Digital Signal Processing DT PCM DM SNR SNDR SHDR SFDR FIR IIR LPF HPF BPF SR MSB LSB CSA Discrete-Time Pulse Code Modulation Delta modulation Signal-to-Noise Ratio Signal-to-Noise and Distortion Ratio Signal-to-Harmonics Distortion Ratio Spurious Free Dynamic Range Finite-Impulse-Response Infinite-Impulse-Response Low Pass Filter High Pass Filter Band Pass Filter Shift Register Most Significant Bit Least Significant Bit Carry Save Adder

6 Contents RCA FPGA ASIC CD ENOB Ripple Carry Adder Field-Programmable Gate Array Application-Specific Integrated Circuit Compact Disc Effective Number of Bits

Chapter 1 Introduction The target of this project is to study and design a mixed-signal processing system consisting of an Analog-to-Digital Converter (ADC), Digital Signal Processor (DSP) and Digital-to-Analog Converter (DAC), for the smart dust application, in a top-down, test-driven design methodology. The complete system has to be operated in a CT mode without any sampling. The focus is to achieve low power consumption and area, without sacrificing the overall system performance. This chapter provides a brief introduction to the thesis work and describes the context of the project. Section 1.1 presents a brief introduction of the smart dust mote, explaining the blocks targeted to be designed in this project. Section 1.2 presents the specifications of the project. Section 1.3 provides the details about the Continuous-Time (CT) processing and section 1.4 mentions the details about the overall project organization. 1.1 Smart dust: A brief introduction There has been a new phenomenon emerging out in recent past called smart dust also known as motes or wireless sensor networks or swarming. Smart dust is a tiny (size and density of a sand particle), ultra-low-power electronic sensory autonomous device packed with various sensors, intelligence and even wireless communication capability. A typical scenario could be smart dust motes deployed in large numbers to form an ad-hoc network, called as swarm, detects environment variables such as light, temperature, pressure, vibration, magnetic flux density or chemical levels. This network, formed by few tens or even millions of motes, can communicate with neighboring motes and pass on the data collected from one mote to another in a systematic way, which can be collected and processed further [1]. Smart dust can derive the energy necessary for its functioning either from batteries or from the environment itself, or from both. The power consumption of the smart dust decreases with the shrinkage in the size of the mote. It has to be in the order of few microwatts. This imposes a stringent constraint on the design, and has to be addressed by following various low power design techniques. Figure 1.1 shows the block level details of a single autonomous smart dust 7

8 Introduction Input/ Control Signal Energy harvest Energy storage Supply regulator Control Input Signal Low-speed Sensor I/F High-speed Sensor I/F Processor Transceiver section Tx Rx Front end Tx/Rx data Figure 1.1: Block diagram of a typical smart dust mote. mote. A typical smart dust module consists of an energy harvester, energy storage, supply regulator, control, high-speed sensor interface, low-speed sensor interface, DSP and radio transceiver section. Energy harvester generates energy from the environment such as solar radiation, wind or even vibration. The generated energy is stored for future usage, using an energy storage element. The available energy is supplied efficiently, in the form of fixed voltages and currents, to the various circuits of the system with the help of the supply regulator. The control circuitry is responsible for the various control mechanisms involved in a mote, which decides the operation of the mote. The sensors collect the environmental variations of interest and convert them to an equivalent electrical signal, analog in nature. The sensory interfaces are required to perform initial signal conditioning and analog to digital conversion of the sensed data. The data is processed digitally using a DSP. DSPs can essentially perform various kinds of operations on the digital signals, such as filtering, domain transformations, compression, encryption, etc. The processed data is reconstructed back to analog equivalent necessary for transmission, using a DAC (not shown in figure). The transceiver section upconverts the baseband signal to Radio Frequency (RF) signals and transmits them. It also receives the RF signals and downconverts them to the baseband singal. This project targets the design of the low speed sensor interface and the DSP, as highlighted in figure 1.1. 1.2 Smart dust: specification The following section presents the specification of the CTDSP system, that is finally going to be deployed in the smart dust motes. The major constraint imposed on the system is that all the blocks in the design should be clockless. Further, the system should be implemented in 65 nm advanced Complimentary Metal Oxide

1.3 Continuous time processing 9 Semiconductor (CMOS) process. The specifications of the ADC, DAC and the transversal direct-form Finite-Impulse-Response (FIR) Low Pass Filter (LPF) is as shown in table 1.1. Table 1.1: CTDSP system specification. Item parameter Min Typ Max Unit ADC Resolution 3 4 8 bits Maximum input signal frequency 20 khz Sampling frequency 44.1 khz Passband edge frequency 5.2 khz LPF Stopband edge frequency 10 khz Passband ripple 1 db Stopband attenuation 30 50 db DAC Resolution 3 4 8 bits Generic Supply voltage 1.2 V Process 65 nm 1.3 Continuous time processing A new emerging field of digital signal processing in CT has been presented by Prof. Yannis Tsividis of Columbia University [2, 3]. It is opposed to the conventional sampled systems where the processing is carried out in discrete time. This CTDSP system processes the data sensed by the analog interface block of the sensor module and produce the output to the RF front-end. As the input data is of burst nature, occurring occasionally, it is highly desirable that the CTDSP system remains idle most of the time and operates only when there is a significant data to process. This is achieved by using level crossing technique, where the ADC operates only if there is a significant variation observed in the input signal. It doesn t produce a sample if there is a long silence or no data available to process. 1.4 Thesis organization The thesis is organized in various chapters as explained below. Chapter 2 presents comparison of CT and conventional DSP system. Advantages and drawbacks of both the systems are described briefly. Chapter 3 provides mathematical treatment, corroborated by MATLAB simulations. The attention is then given to the details of the sub-systems employed in the ED DSP system, ADC, DSP and DAC. Various different architectures are discussed for the three sub-systems and designs suitable for implementation are chosen. Chapter 4, 5 and 6 elaborates the implementation details of each sub-system CTADC, CTDSP and CTDAC, respectively. Detailed descriptions of various ar-

10 Introduction chitectures of the sub-blocks with the simulation results at various design stages are shown. Chapter 7 presents the CTDSP system top level simulation results. Chapter 8 presents the future work and conclusions.

Chapter 2 Conventional versus Event-driven systems Signal processing is needed to derive the information content present in the sensed real-world signals. The real-world signals are analog in nature, i.e., continuous in time and amplitude. These signals can be processed by using analog or digital signal processing. A mix of both techniques can also be used, which is known as mixed-signal processing [4]. With the advent of digital computers, backed up by large scale integration of the circuits, digital signal processing has revolutionized the world. Conventionally, the digital signal processing is done only in the discretetime, with the help of a sampling clock. Hence, conventional DSP systems are also known as sampled data systems. Recently, it has been experimentally shown by Tsividis et al. [2, 5], that the signal processing in digital domain can also be performed in Continuous-Time (CT) domain. These systems are called as CT or ED DSP systems. In this chapter the basic principle of operation of the conventional clocked and CTDSP systems are presented. The level-crossing quantization technique used in the CT system is briefly explained. The advantages and drawbacks of the two systems are outlined. The chapter is concluded with a comparison of the clocked system to the CT system. The future chapters are based on the motivations and conclusions drawn from the discussions presented in this chapter. 2.1 Conventional clocked DSP systems A conventional DSP system operates with a global reference or clock signal. The input signal, x(t), is sampled-and-quantized at the rising or falling edge of the clock signal for an edge triggered system. The quantized signal is encoded digitally and processed by the subsequent DSP section. The overall system is completely synchronized with respect to the global clock. In the subsequent sections a detailed description of the conventional clocked system is presented. 11

12 Conventional versus Event-driven systems clk x(t) Conventional DSP system y s (t) Figure 2.1: Block diagram of the conventional clocked DSP system. 2.1.1 Introduction to the conventional clocked DSP systems For the clocked DSP systems, the frequency of operation, known as the clock frequency, is limited by the Nyquist criteria or sampling theorem, which states that the sampling rate must be greater than twice the bandwidth of the input signal as given by [4] f s > 2 f b, (2.1) where f s is the sampling frequency and f b is the bandwidth or maximum frequency of the input signal. A simple block diagram of the conventional DSP system is shown in figure 2.1 with the input and output signal description given in table 2.1. As shown in figure 2.2, the conventional clocked DSP system can be further divided into three sub-systems: the ADC, DSP and DAC. The description of the input and output signal is provided in table 2.2. The ADC is the first block of the DSP system, which samples and quantizes the input signal, x(t), followed by encoding to produce the digital binary data, b i (n). This digitized data is provided to the DSP sub-section, which process it based on the defined functionality, like low-pass, high-pass or band-pass filtering, domain transformation, encryption, etc. The digitally processed data, d j (n), from the DSP section is provided to the output DAC, which reconstructs it back to the analog equivalent, y s (t), where the subscript s represents sampled system output. Table 2.1: Signal description for the conventional clocked DSP system as shown in figure 2.1. Signal Description Type (Input/ Output) x(t) Input signal Input clk Global clock signal Input y s (t) Output signal Output

2.1 Conventional clocked DSP systems 13 Table 2.2: Signal description for the conventional clocked DSP system with an ADC-DSP-DAC sub-systems as shown in figure 2.2. Signal Description Type (Input/ Output) x(t) Input signal Input clk Global clock signal Input b i (n) ADC out to DSP, Digitally encoded binary signal Intermediate signal (In/out) d j (n) DSP out to DAC, Digitally processed binary signal Intermediate signal (In/out) Y s (t) Output signal Output 2.1.2 Operational details of the conventional clocked DSP systems As mentioned in the previous section, the operation of the conventional clocked DSP systems can be classified as sampling and quantization followed by the digitization, processing of the binary data by the DSP and the reconstruction of the digital signal to the analog equivalent by the output DAC. These operations are explained in detail in the following sections. 2.1.2.1 Sampling, quantization and digital encoding As shown in Fig. 2.2, the ADC is the first sub-system of the conventional DSP system, which converts the input signal, x(t), to the digital equivalent, b i (n), where n represents the time in the discrete domain. The complete operation can be divided into two steps: Sample-and-hold and quantization, and Digitization. Fig. 2.3(a) presents the sampling operation. The input signal is sampled at regular interval of 1/f s and the samples are held for one cycle. The data samples are quantized to the nearest pre-defined quantization level by the quantizer. This is clk clk clk x(t) b i (n) d j (n) y s (t) ADC DSP DAC Figure 2.2: Conventional clocked DSP system with the basic building blocks ADC- DSP-DAC, each sub-system is controlled through the global clock signal.

14 Conventional versus Event-driven systems Quantization levels x(t) Quantization level Sampling Instances Quantization levels x(t) xq(t) Quantization level Sampling Instances ti-1 ti (a) t ti-1 ti (b) t Figure 2.3: Conventional clocked DSP system: (a) sampling (shown by black dots in figure), and (b) quantization (x q (t), also known as amplitude quantization). known as amplitude quantization and is shown in fig. 2.3(b). The quantized data, x q (t), as shown in fig. 2.3(b), is also known as L-ary digital signal, where L is the total number of quantization levels [6]. The L-ary data can be processed directly by the subsequent DSP section, but it is more practical to have binary signal as an input to the DSP section because of the involved simplicity and the ease of processing. Therefore, L-ary, x q (t), is converted to binary signal, b i (n), using the pulse coding technique [6]. Figure 2.4 shows a 3-bit representation b 0, b 1 and b 2 of the quantized signal, x q (t). In general, N-bit system has N-binary output lines. The above discussion is based on the most widely used modulation technique called the pulse code modulation. There are other modulation techniques like differential pulse code modulation, delta modulation, adaptive delta modulation, etc., which can be employed to have different binary output representation. The sampling and quantization generates noise floor in the output spectrum of the signal which is explained next [7 9]. Consider a sinusoidal signal with an input frequency, f b, and sampling frequency, f s. The sampling operation forms the replica s of the input signal at (n f s ± f b ), where n is an integer. This multi-tone signal is passed through the quantizer. The quantizer produces the harmonics of each frequency component along with their inter-modulation components. These harmonics and the inter-modulation terms are spread across the spectrum, including the in-band and hence, resulting in the formation of the quantization noise floor. The Signal-to-Noise Ratio (SNR) due to the noise floor is given by the classical formula [10]: SNR(dB) = 6.02 N + 1.76, (2.2) where N is the number of bits or resolution of the ADC. As mentioned in section 2.1.1, the minimum clock frequency is limited by the Nyquist theorem. If the sampling criterion, given by equation 2.1, is not met,

2.1 Conventional clocked DSP systems 15 x t x q t Quantization level Sampling instances Amplitude t b0 b1 b2 t i-1 t i t Figure 2.4: Conventional clocked DSP system with sampling and quantization and 3-bit digital output representation; b 0, b 1 and b 2. than the higher frequency components will fold back into the band of interest and corrupt the data. This condition is known as spectral-folding or aliasing. A special filter known as an anti-aliasing filter with cutoff frequency half the sampling frequency (f s /2, also known as the folding frequency) is required to band-limit the input signal, before taking the samples. If an anti-aliasing filter is not used, then any data in the region f s /2 ± f x will be corrupted, where f x is overlapping tail of the spectrum above f s /2. Additional techniques are required to recover the corrupted data, which demands for an extra hardware. Note: The practical signals are in general time-limited in nature. It means, that the bandwidth of the signal is infinite (time-limited signals have infinite bandwidth whereas band-limited signals have infinite duration, a practical signal cannot be time-limited and band-limited at the same time [6]). As mentioned above, the sampling results in the formation of the replicas of the original signal and each replica will have tails spread to infinity due to infinite bandwidth. These tails are always folded back to the band of interest, even if the Nyquist criterion is followed. 2.1.2.2 Conventional digital signal processing and reconstruction The input to the DSP section is the digitized binary data, b i (n), from the ADC section. Based on the application, the DSP system can be designed to perform the

16 Conventional versus Event-driven systems operations like frequency filtering, domain transformations, compression, encryption, etc. The discussion here is based on the filters, which are in general, used to select the frequency band of interest (Low-pass, high-pass, band-pass or band reject). The filter can be Finite-Impulse-Response (FIR) type or Infinite-Impulse- Response (IIR) type, with their transfer function given as [11]: H (z) = k=0 M 1 h [k] z k, (2.3) H (z) = P (z) D (z) = p 0 + p 0 z 1 + p 1 z 2 + 1 + d 0 z 1 + d 1 z 2 +, (2.4) respectively. The digitally processed data, d j (n), is provided to the output DAC which reconstructs it back to an analog equivalent. There are many different architectures of the DAC which can be used like the binary weighted, thermometercoded, linear-coded, hybrid, etc. Based on the speed and resolution of the system, the circuit level realization of the DAC can be done in the voltage-mode, currentmode or charge-redistribution-mode. Different implementation schemes like the current-steering, charge-redistribution, R-2R ladder, resistor-string or switchedcurrent algorithmic DAC can be employed for the circuit level design of the DAC [12]. These DACs can be further modified as segmented versions to achieve lesser hardware [13]. The clock frequency, f s, in general, are kept same for the ADC, DSP and the DAC section. But it is possible to design multi-rate systems where different blocks operates at different frequency. It can be done by increasing the data rate using an interpolator (frequency up-converter used before the DAC) and bringing it down by the decimator (frequency down-converter used after the ADC and before providing the samples to the DSP) [11, 14]. The ADC and DAC obtained using these techniques are also known as oversampled data converters. The interpolator and decimator blocks are part of the DSP core. 2.1.3 Advantages of conventional DSP systems Synchronized DSP system implementation is a vast topic with lot of research effort already put into it, since its inception. Few major advantages of the conventional DSP systems are as follows: The main advantage is the ease of designing the system. The sampling clock period is primarily governed by the critical path of the system, which when decided upon can lead to faster implementation of the system. Used in many applications for rapid implementation of complex DSP algorithms, for example, using general purpose DSP processor or even on general purpose processor. Availability of the design tools to synthesize even advanced optimized DSP algorithms on FPGA as well as ASIC designs and automate whole design process of DSP processor.

2.1 Conventional clocked DSP systems 17 Since the data available is sampled at particular sampling rate defined by the system, for example, in CD, the audio is sampled at a sampling rate of 44.1 khz, storage and retrieval of data becomes easier and cheaper. Few major drawbacks of the conventional clocked systems are discussed in the next section. 2.1.4 Drawback of the conventional DSP systems The drawbacks of the conventional DSP systems are as described below: A sampled system requires clock generator, which has a large fan-out, since it has to drive gates of many transistors. Hence, making it costly to implement, both in terms of the area and power consumption. The sampling frequency is decided based on the highest frequency component of the input signal. It is therefore necessary to implement a band-limiting filter, known as an anti-aliasing filter, to avoid aliasing, whose implementation might also be a costly affair. The sampling results in the aliasing of higher frequency terms to the band of interest, even if the Nyquist theorem is followed. The sampling and processing of the data with long silence or no change in the signal results in the wastage of power. This can be mitigated using techniques such as clock gating at the expense of additional hardware. This may decrease dynamic power dissipation, but shall add up to the static power consumption of leakage and obvious area ascension. Hence, conventional DSP system is not apt for applications where signals occur in bursts, with high silence percentage, especially for the wireless sensor motes driven by a small battery, demanding large battery lifetime. The deviation from the precise sample timing instances due to the clock jitter and the clock skew can cripple down the system performance to undesired levels, if not designed properly. The signal to be processed by the smart dust module is of burst nature, which occurs occasionally. The clocked systems, although equipped with many advantages, are not an ideal choice for processing the burst-like signals. The drawbacks listed for the clocked system are more dominating compared to the advantages for the smart dust application. In the next section event-driven CT digital signal processing systems are discussed, which operates on the principle of level-crossing and are very suitable for burst-type data processing.

18 Conventional versus Event-driven systems 2.2 Continuous-time or event-driven DSP systems 2.2.1 Introduction to the CTDSP systems The CT or event-driven Digital Signal Processor (DSP) systems, as the name suggests, operates in continuous time mode [2, 9]. The input signal, x(t), is processed by the CTDSP system to produce output, y(t). There is no clock involved anywhere in the system. A simple block diagram of a CTDSP system is shown in figure 2.5 with the input and output signal description given in table 2.3. x(t) CTDSP system y(t) Figure 2.5: Block diagram of the continuous-time (CT) DSP system. Table 2.3: Signal description for continuous-time (CT) system as shown in figure 2.5. Signal Description Type (Input/ Output) x(t) CT input signal Input y(t) CT output signal Output Similar to the conventional clocked systems, a CT system can also be divided into three basic sub-systems: the CTADC, CTDSP and CTDAC. As pointed out above, there is no global clock involved anywhere in CTDSP system. Hence, all the three blocks operates in a CT mode and are represented with a prefix CT [7, 15]. Figure 2.6 shows the block diagram of the CTDSP system with the three sub-systems and table 2.4 presents the description of the input and output signals. CTADC is the first block in the CTDSP system which quantizes and digitizes the input signal, x(t), to a CT output, b i (t). Unlike conventional system, the input signal is not sampled before quantization. The CT data is then processed by the CTDSP sub-system to produce digital data, d j (t), which is reconstructed to analog signal, y(t), by the CTDAC block. Note that the time domain is represented in t as it is always continuous in nature. In the next section operational details of the CTDSP system is presented. The level-crossing approach, as used in CT system, is explained and the advantages and drawbacks are described.

2.2 Continuous-time or event-driven DSP systems 19 Table 2.4: Signal description for the CTDSP system with the CTADC-CTDSP- CTDAC sub-systems as shown in figure 2.6. Signal Description Type (Input/ Output) x(t) CT input signal Input b i (t) ADC output to DSP, CT digitally encoded binary signal Intermediate signal (In/out) d i (t) DSP output to DAC, CT digitally processed binary signal Intermediate signal (In/out) y(t) CT output signal Output 2.2.2 Operational details of the CTDSP system The CTDSP system adopts nonuniform sampling approach, where samples are generated only when the event crosses predefined quantization reference level. The operation of the CTDSP system can be classified as quantization by the CTADC block and the processing of the digital (continuous) data by the CTDSP subsystem. The next section presents the details of these operations. 2.2.2.1 CTDSP quantization technique: A level-crossing approach A conventional DSP system adopts uniform quantization technique, where samples are taken and processed at every clock cycle. The maximum frequency of the input signal dictates the minimum possible clock frequency of sample generation. However, it turns out that, for signals with burst-like nature and long period of silence, exhaustive sampling is not required as done in conventional systems. The samples generated either contains no information or repetitive information. Further, additional dynamic power is required for the processing of these samples by the DSP section. A different class of the quantization technique, called a level-crossing sampling scheme, is suggested by Sayiner et al., [16] and further explained by Tsividis in [2, 3, 7]. It is a nonuniform sampling approach, where the samples are generated only when the event crosses the predefined quantization reference level. Since the quantization is based on the event and is continuous in time, it is called as an x(t) b i (t) d j (t) y(t) CTADC CTDSP CTDAC Figure 2.6: CTDAC. CTDSP system with the basic building blocks CTADC-CTDSP-