Digitalteknik EIT020 Lecture 16: Design av digitala kretsar November 10, 2014
Digitalteknikens kopplingar mot andra områden Mjukvara Hårdvara Datorteknik Kretskonstruktion Digitalteknik Elektronik Figure:, Digitalteknik L16:2,
DEL 3 - Digital kretskonstruktion Hur hanterar vi en konstruktion som innehåller miljoner transistorer? Vilken typ av konstruktion ska vi välja, en processor, en FPGA eller en ASIC? Hur beskriver vi konstruktionen på ett stukturerat sätt?, Digitalteknik L16:3,
Klassicering av integrerade kretsar Tillverkning kräver hög kompetens och stora resurser. Därför nns endast ett litet antal halvledarfabrikanter i världen. Kundspecika kretsar (ASIC, application specic integrated circuits) Standardkretsar (FPGA, eld programmable gate array), Digitalteknik L16:4,
ASIC Full-custom ASIC, kunden levererar en fullständig specikation ner på lägsta nivån (transistor). Mycket komplex design. Standard-cell ASIC, Kunden beskriver sin design i form av standardceller, givna av tillverkaren. Allt från enkla grindar till microprocessorer. Gate array ASIC, Chipet har stora grindmatriser, där kunder specicerar förbindningsmönster., Digitalteknik L16:5,
Standardkretsar Funktionsbestämda: fabricerade komponenter (7400 serien med olika komponenter), mikroprocessorer, etc. Icke funktionsbestämda: PLD (programmable logic device), enkla programmerbara komponenter (PLA, PAL, ROM); Complex eld programmable devices, CPLD (complex programmable logic device) FPGA, Digitalteknik L16:6,
FPGA Integrerad krets, vars fysiska funktion kan ändras genom att ny programmering översänds genom anslutning av en enkel kabel. Kretsens funktionsbeskrivning kan laddas in direkt via en datalänk (JTAG) till en dator eller från minnen som till exempel RAM, ROM eller ashminne. Vissa FPGA-kretsar behåller kongurationen även efter förlust av elektrisk spänning., Digitalteknik L16:7,
17 7 Series FPGAs Overview DS180 (v1.16) October 8, 2014 Product Specification General Description Xilinx 7 series FPGAs comprise three new FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 series FPGAs include: Artix -7 Family: Optimized for lowest cost and power with small Virtex -7 Family: Optimized for highest system performance and form-factor packaging for the highest volume applications. capacity with a 2X improvement in system performance. Highest capability devices enabled by stacked silicon interconnect (SSI) Kintex -7 Family: Optimized for best price-performance with a 2X technology. improvement compared to previous generation, enabling a new class of FPGAs. Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs. Summary of 7 Series FPGA Features Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory. 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering. High-performance SelectIO technology with support for DDR3 interfaces up to 1,866 Mb/s. High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to maximum rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces. A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors. DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering. Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter. Integrated block for PCI Express (PCIe), for up to x8 Gen3 Endpoint and Root Port designs. Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction. Low-cost, wire-bond, lidless flip-chip, and high signal integrity flipchip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option. Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power. Table 1: 7 Series Families Comparison Maximum Capability Artix-7 Family Kintex-7 Family Virtex-7 Family Logic Cells 215K 478K 1,955K Block RAM (1) 13 Mb 34 Mb 68 Mb DSP Slices 740 1,920 3,600 Peak DSP Performance (2) 929 GMAC/s 2,845 GMAC/s 5,335 GMAC/s Transceivers 16 32 96 Peak Transceiver Speed 6.6 Gb/s 12.5 Gb/s 28.05 Gb/s Peak Serial Bandwidth (Full Duplex) 211 Gb/s 800 Gb/s 2,784 Gb/s PCIe Interface x4 Gen2 x8 Gen2 x8 Gen3 Memory Interface 1,066 Mb/s 1,866 Mb/s 1,866 Mb/s I/O Pins 500 500 1,200 I/O Voltage 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V Package Options, Digitalteknik L16:8, Low-Cost, Wire-Bond, Lidless Flip-Chip Notes: 1. Additional memory available in the form of distributed RAM. Low-Cost, Lidless Flip-Chip and High-Performance Flip-Chip Highest Performance Flip-Chip
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2014-11-07 Digilent Inc. - Digital Design Engineer's Source Digilentinc.com Blog Learn Forum search digilentinc.com Search Products +Coming Soon +New Products FPGA Boards Cmod S6 ZYBO ZedBoard Anvyl Genesys Atlys Nexys 4 Nexys 3 Nexys 2 Basys 3 Basys 2 NetFPGA-1G-CML FMC Carrier S6 XUP V5 S3E Board CoolRunner-II Starter XUP V2-Pro NETFPGA Cmod +Scopes & Instruments +chipkit Boards +Microprocessor Boards +FMC Cards +Peripheral Modules +NI Academic Products +Analog Devices +Microchip Tools +Software +Programming Solutions +Robotic Platforms +Textbooks +Add-On Boards +Accessories +Discontinued Enter a value code: Submit Nexys 4 Artix-7 FPGA Board $320.00 $159.00 Currently in stock Part # 410-274P-KIT Hide Details The Nexys4 board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7 Field Programmable Gate Array (FPGA) from Xilinx. With its large, high-capacity FPGA (Xilinx part number XC7A100T- 1CSG324C), generous external memories, and collection of USB, Ethernet, and other ports, the Nexys4 can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, temperature sensor, MEMs digital microphone, speaker amplifier and lots of I/O devices allow the Nexys4 to be used for a wide range of designs without needing any other components. The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more resources than earlier designs. Artix-7 100T features include: 15,850 logic slices, each with four 6-input LUTs and 8 flip-flops 4,860 Kbits of fast block RAM Six clock management tiles, each with phase-locked loop (PLL) 240 DSP slices Internal clock speeds exceeding 450MHz On-chip analog-to-digital converter (XADC) The Nexys4 also offers an improved collection of ports and peripherals, including: 16 user LEDs Two 4-digit 7-segment displays 16 user switches Two tri-color LEDs Micro SD card connector USB-UART Bridge PWM audio output PDM microphone 12-bit VGA output Temperature sensor 10/100 Ethernet PHY 3-axis accelerometer Serial Flash Four Pmod ports 16Mbyte CellularRAM Digilent USB-JTAG port for FPGA USB HID Host for mice, keyboards and Pmod for XADC signals programming and communication memory sticks The Nexys4 is compatible with Xilinx s new high-performance Vivado Design Suite as well as the ISE toolset, which includes ChipScope and EDK. Xilinx offers free Webpack versions of these toolsets, so designs can be implemented for no additional cost. If you would like an evaluation board for academic purposes, you can apply for a donation through the Xilinx University Program. Note: The Nexys4 s onboard programming circuitry is not supported by the Hardware Server in Vivado 2013.2 and earlier. The FPGA must be programmed using impact in these versions of Vivado. The Hardware Server in versions 2013.3 and newer fully support the Nexys4., Digitalteknik L16:10,
, Digitalteknik L16:11, Nexys 4 development board
Utvecklingsprocessen - Abstraktionsnivå Låg nivå Hög nivå Transistor nivå Grind nivå (timing - propagation delay; placement and routing on the chip) RTL (Register Transfer Level) nivå (moduler konstruerade från grindar/vippor) (abstrakta datatyper; beteendebeskrivning; gemensam klocksignal; stabila system; layout - oor plan) Processor nivå (större mer avancerade block), Tillverkare tillhandahåller IP's, exempelvis en microprocessor, Digitalteknik L16:12,
Utvecklingsprocessen - CAD CAD-verktyg används för att konstruera kretsar. Ett CAD-verktyg är ett datorprogram som automatiskt gör delar av konstruktionsarbetet. CAD-verktyg behöver en beskrivning av kretsens funktion på någon abstraktionsnivå. HDL (Hardware Description Language), exempelvis VHDL, Verilog, Digitalteknik L16:13,
Utvecklingsprocessen - CAD CAD-programmen kan göra följande Syntes - Översättning av beskrivningen på högre nivå till lägre nivå, för att till slut syntetisera till en färdig krets. Fysisk design beror på underliggande krets, exempelvis vilken FPGA som används. Veriering - På varje abstraktionsnivå kan veriering av beteendet av beskrivningen ske. Funktionsmässig veriering Timing veriering Simulering - utifrån dokumenterade önskemål analyserar CAD-programmet Testning (fysisk), funktionen hos varje färdig krets testas för att upptäcka defekter etc., Digitalteknik L16:14,